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    Systems and methods for statistical static timing analysis
    13.
    发明授权
    Systems and methods for statistical static timing analysis 有权

    公开(公告)号：US10185795B1

    公开(公告)日：2019-01-22

    申请号：US15290356

    申请日：2016-10-11

    Applicant: Cadence Design Systems, Inc.

    Inventor： Igor Keller ,  Praveen Ghanta ,  Arun Kumar Mishra

    IPC: G06F17/50

    Abstract: Electronic design automation systems, methods, and media are presented for characterizing on-chip variation of circuit elements in a circuit design using statistical values including skew, and for performing statistical static timing analysis using these statistical values. One embodiment models delay characteristics under certain operating conditions for circuit elements with asymmetric (e.g., non-Gaussian) probability density functions using normalized skewness. The modeled delay can then be used to perform various timing analysis operations.

    Method and system for timing analysis with adaptive timing window optimization for determining signal integrity impact
    14.
    发明授权
    Method and system for timing analysis with adaptive timing window optimization for determining signal integrity impact 有权

    公开(公告)号：US09881123B1

    公开(公告)日：2018-01-30

    申请号：US15198635

    申请日：2016-06-30

    Applicant: CADENCE DESIGN SYSTEMS, INC.

    Inventor： Ratnakar Goyal ,  Manuj Verma ,  Igor Keller ,  Arvind Nembili Veeravalli

    IPC: G06F9/455 ,  G06F17/50

    CPC classification number: G06F17/5031 ,  G06F2217/82

    Abstract: A method and system are provided for timing analysis of an electronic circuit design. A timing graph defines a plurality of timing paths through different subsections of the electronic circuit design. A timing window is defined for each of the nodes included in a timing path. At least one preliminary round of a predetermined signal integrity analysis is executed on the circuit design based on the timing windows to identify at least one pair of crosstalk-coupled victim and aggressor nodes. Each victim node's timing window is adaptively adjusted according to a predetermined timing property thereof. At least one primary round of the predetermined signal integrity analysis is executed on the electronic circuit design based in part on this adaptively adjusted timing window for each victim node to generate a delay, which is annotated to the timing graph. A predetermined static timing analysis is executed based on the delay-annotated timing graph.

    View data sharing for efficient multi-mode multi-corner timing analysis
    15.
    发明授权
    View data sharing for efficient multi-mode multi-corner timing analysis 有权
    查看数据共享，实现高效多模式多角时序分析

    公开(公告)号：US09384310B1

    公开(公告)日：2016-07-05

    申请号：US14502611

    申请日：2014-09-30

    Applicant: Cadence Design Systems, Inc.

    Inventor： Igor Keller ,  Jijun Chen ,  Pradeep Yadav

    IPC: G06F17/50

    CPC classification number: G06F17/5031 ,  G06F2217/84

    Abstract: A system and method for performing multi-mode multi-corner (MMMC) analysis such that multiple views or conditions can be analyzed together to improve runtime by taking advantage of common steps of analysis in different corners. Views are clustered based on their similarity to one another to take advantage of calculations and other tasks that may be shared between views during timing analysis. Then, during timing analysis, each net in the design is analyzed for each view.

    Abstract translation: 一种用于执行多模式多角度（MMMC）分析的系统和方法，使得可以一起分析多个视图或条件以通过利用不同角落中的常见分析步骤来改善运行时间。 视图是基于彼此的相似性进行聚类，以利用在时序分析期间可以在视图之间共享的计算和其他任务。 然后，在时序分析期间，为每个视图分析设计中的每个网络。

    Static timing analysis of integrated circuit designs with flexible noise and delay models of circuit stages
    16.
    发明授权
    Static timing analysis of integrated circuit designs with flexible noise and delay models of circuit stages 有权
    集成电路设计的静态时序分析，具有灵活的噪声和电路阶段的延迟模型

    公开(公告)号：US09129078B1

    公开(公告)日：2015-09-08

    申请号：US14067720

    申请日：2013-10-30

    Applicant: Cadence Design Systems, Inc.

    Inventor： Igor Keller ,  Vinod Kariat ,  King Ho Tam

    IPC: G06F17/50

    CPC classification number: G06F17/5031 ,  G06F17/5036 ,  G06F17/5068 ,  G06F17/5072 ,  G06F2217/82 ,  G06F2217/84

    Abstract: Systems, apparatus, and methods of static timing analysis for an integrated circuit design in the presence of noise are disclosed. The integrated circuit design may be partitioned into a plurality of circuit stages. A timing graph including timing arcs is constructed to represent the timing delays in circuit stages of the integrated circuit design. A model of each circuit stage may be formed including a model of a victim driver, an aggressor driver, a victim receiver, and a victim net and an aggressor net coupled together. For each timing arc in the timing graph, full timing delays may be computed for the timing arcs in each circuit stage.

    Abstract translation: 公开了在存在噪声的情况下用于集成电路设计的静态时序分析的系统，装置和方法。 集成电路设计可以被划分成多个电路级。 包括定时弧的定时图被构造成表示集成电路设计的电路阶段中的时序延迟。 可以形成每个电路级的模型，其包括耦合在一起的受害者驱动器，攻击者驱动器，受害者接收器以及受害者网络和侵略者网络的模型。 对于定时图中的每个定时电弧，可以为每个电路级中的定时弧计算全定时延迟。

    Static timing analysis methods for integrated circuit designs using a multi-CCC current source model
    17.
    发明授权
    Static timing analysis methods for integrated circuit designs using a multi-CCC current source model 有权
    使用多CCC电流源模型的集成电路设计的静态时序分析方法

    公开(公告)号：US08966421B1

    公开(公告)日：2015-02-24

    申请号：US14023450

    申请日：2013-09-10

    Applicant: Cadence Design Systems, Inc.

    Inventor： Vinod Kariat ,  Igor Keller ,  Joel R. Phillips ,  King Ho Tam

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5036 ,  G06F2217/84

    Abstract: In one embodiment of the invention, a multi-CCC current source model is disclosed to perform statistical timing analysis of an integrated circuit design. The multi-CCC current source model includes a voltage waveform transfer function, a voltage dependent current source, and an output capacitor. The voltage waveform transfer function receives an input voltage waveform and transforms it into an intermediate voltage waveform. The voltage dependent current source generates an output current in response to the intermediate voltage waveform. The output capacitor is coupled in parallel to the voltage dependent current source to generate an output voltage waveform for computation of a timing delay.

    Abstract translation: 在本发明的一个实施例中，公开了一种多CCC电流源模型来执行集成电路设计的统计时序分析。 多CCC电流源模型包括电压波形传递函数，电压相关电流源和输出电容器。 电压波形传递函数接收输入电压波形并将其转换为中间电压波形。 电压相关电流源响应于中间电压波形产生输出电流。 输出电容器并联到与电压相关的电流源，以产生用于计算定时延迟的输出电压波形。

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