公开(公告)号：US06772359B2

公开(公告)日：2004-08-03

申请号：US09725896

申请日：2000-11-30

申请人： Jong Tae Kwak ,  Dong Woo Shin ,  Jong Sup Baek ,  Choul Hee Koo ,  Nak Kyu Park

发明人： Jong Tae Kwak ,  Dong Woo Shin ,  Jong Sup Baek ,  Choul Hee Koo ,  Nak Kyu Park

IPC分类号： G06F104

CPC分类号： G06F1/3275 ,  G06F1/3203 ,  G11C7/22 ,  G11C11/4076 ,  Y02D10/13 ,  Y02D10/14

摘要： A clock control circuit for a Rambus DRAM is provided which reduces power consumption by determining in advance whether an applied command is a read or current control command, and enabling a clock signal for externally outputting an internal data only during the read or current control command. Our circuit includes: an input signal detecting unit for generating an enable signal when one of a first comparing signal comparing an address value of the selected Rambus DRAM with a device address value of a COLC packet, and a second comparing signal comparing the address value of the selected Rambus DRAM with a device address value of a COLX packet is enabled, and when the command is a read or current control command; a signal generating unit for generating a clock enable signal for externally outputting an internal data when one of the first and second comparing signals is enabled; an output signal maintaining unit for outputting a control signal for maintaining the clock enable signal to the signal generating unit in the read or current control command; and an output signal control unit for outputting a control signal for controlling generation of the clock enable signal to the signal generating unit, when the command is not the read or current control command.

摘要翻译： 提供了一种用于Rambus DRAM的时钟控制电路，其通过预先确定所应用的命令是读取还是当前控制命令来降低功耗，并且仅在读取或当前控制命令期间启用用于外部输出内部数据的时钟信号。 我们的电路包括：输入信号检测单元，用于当将所选择的Rambus DRAM的地址值与COLC分组的设备地址值进行比较的第一比较信号中的一个产生使能信号，以及第二比较信号， 所选择的具有COLX分组的设备地址值的Rambus DRAM被使能，并且当命令是读取或当前控制命令时; 信号产生单元，用于当所述第一和第二比较信号之一被使能时，产生用于外部输出内部数据的时钟使能信号; 输出信号维持单元，用于在读取或当前控制命令中输出用于将时钟使能信号保持到信号生成单元的控制信号; 以及输出信号控制单元，用于当命令不是读取或当前控制命令时，向信号生成单元输出用于控制产生时钟使能信号的控制信号。

公开(公告)号：US06442077B2

公开(公告)日：2002-08-27

申请号：US09751394

申请日：2001-01-02

申请人： Dong Woo Shin

发明人： Dong Woo Shin

IPC分类号： G11C700

CPC分类号： G11C7/24 ,  G11C7/1045 ,  G11C11/4076 ,  G11C11/4078

摘要： The inventions herein feature an arrangement for controlling read and write operations in a semiconductor memory device, which can reduce power consumption by controlling data read and write operations in a DRAM having an open drain output buffer. The circuit for controlling the read and write operations in the semiconductor memory device includes a write unit for comparing potential states of bits of a write data according to a control signal, converting the write data into a first logic level and writing the converted data on DRAMs as an internal data with a flag bit having a first logic level, when a number of the bits having the first logic level is greater than a number of the bits having a second logic level, and writing the write data on the DRAMs as an internal data with a flag bit having the second logic level, when the number of the bits having the first logic level is equal to or smaller than the number of the bits having the second logic level. A read unit reads a read data read from the DRAMs, or converts the read data and reads the converted data according to the potential state of the flag bit.

摘要翻译： 本发明的特征在于一种用于控制半导体存储器件中的读和写操作的装置，其可以通过控制具有开漏输出缓冲器的DRAM中的数据读和写操作来降低功耗。 用于控制半导体存储器件中的读和写操作的电路包括写入单元，用于根据控制信号比较写入数据的位的电位状态，将写入数据转换成第一逻辑电平并将转换的数据写入DRAM 作为具有第一逻辑电平的标志位的内部数据，当具有第一逻辑电平的位的数量大于具有第二逻辑电平的位的数量时，并将写数据写入DRAM作为内部 当具有第一逻辑电平的比特数等于或小于具有第二逻辑电平的比特数时，具有具有第二逻辑电平的标志位的数据。 读取单元读取从DRAM读取的读取数据，或者转换读取的数据，并根据标志位的潜在状态读取转换的数据。

公开(公告)号：US08481161B2

公开(公告)日：2013-07-09

申请号：US11589783

申请日：2006-10-31

申请人： Jong Jin Park ,  Sung Woong Kim ,  Dong Woo Shin ,  Sang Hoon Park

发明人： Jong Jin Park ,  Sung Woong Kim ,  Dong Woo Shin ,  Sang Hoon Park

IPC分类号： B32B5/16 ,  B32B33/00 ,  G03C1/52 ,  G03C1/73

CPC分类号： H05K1/097 ,  B05D1/185 ,  B22F1/0059 ,  B22F2998/00 ,  C03C17/007 ,  C03C2217/42 ,  C03C2217/445 ,  C03C2217/479 ,  C03C2218/33 ,  C09D11/30 ,  H05K2201/0239 ,  Y10T428/25 ,  Y10T428/256 ,  Y10T428/2991 ,  B22F1/0018

摘要： A printable metal nanoparticle having a self-assembled monolayer (SAM) composed of a compound containing a thiol (—SH), isocyanide (—CN), amino (—NH2), carboxylate (—COO) or phosphate group, as a linker, formed on the surface thereof, and a method for formation of a conductive pattern using the same are provided. The metal nanoparticles of an exemplary embodiment can be easily formed into a conductive film or pattern by a printing method, and the resulting film or pattern exhibits excellent conductivity which optimally may be adjusted if desired. Therefore, the resulting metal nanoparticles of can be used to advantage in the fields such as antistatic washable sticky mats, antistatic shoes, conductive polyurethane printer rollers, electromagnetic interference shielding materials, etc.

摘要翻译： 具有由含有硫醇（-SH），异氰化物（-CN），氨基（-NH 2），羧酸酯（-COO）或磷酸酯基的化合物组成的自组装单层（SAM）作为接头的可印刷金属纳米颗粒， 在其表面上形成，并且提供了使用其形成导电图案的方法。 可以通过印刷方法将示例性实施方案的金属纳米颗粒容易地形成为导电膜或图案，并且所得到的膜或图案显示出优异的导电性，如果需要，其可最佳地调节。 因此，所得金属纳米粒子可用于抗静电可洗粘垫，抗静电鞋，导电聚氨酯打印辊，电磁干扰屏蔽材料等领域。

公开(公告)号：US07085882B2

公开(公告)日：2006-08-01

申请号：US10695532

申请日：2003-10-28

申请人： Sun Hyoung Lee ,  In Sun Yoo ,  Dong Woo Shin

发明人： Sun Hyoung Lee ,  In Sun Yoo ,  Dong Woo Shin

IPC分类号： G06F12/00

CPC分类号： G11C11/40615 ,  G11C11/406 ,  G11C11/40618 ,  G11C2211/4062

摘要： Disclosed herein are an SRAM-compatible memory and method of driving the SRAM-compatible memory. The SRAM-compatible memory has memory banks, a parity generator and a parity bank. The memory banks each store corresponding one of input data in its DRAM cells specified by an input address. The memory banks perform write operations independently such that when a refresh operation or a write operation for a previous frame is being performed with respect to DRAM cells of a certain memory bank, the write operation of the input data is independently performed with respect to the respective memory banks except for the certain memory bank. The parity generator generates a input parity determined based on the input data and a certain preset parity value. The parity bank stores the input parity.

摘要翻译： 这里公开了SRAM兼容存储器和驱动SRAM兼容存储器的方法。 SRAM兼容存储器具有存储体，奇偶校验发生器和奇偶校验库。 存储体每个存储由输入地址指定的其DRAM单元中的输入数据之一。 存储体独立地执行写入操作，使得当相对于某个存储体的DRAM单元执行针对先前帧的刷新操作或写入操作时，输入数据的写入操作相对于相应的 记忆库除了某个记忆库。 奇偶校验发生器产生基于输入数据和某个预设奇偶校验值确定的输入奇偶校验。 奇偶校验库存储输入奇偶校验。

公开(公告)号：US5745731A

公开(公告)日：1998-04-28

申请号：US621061

申请日：1996-03-22

申请人： Min Hwahn Kim ,  Dong Woo Shin

发明人： Min Hwahn Kim ,  Dong Woo Shin

IPC分类号： G06F5/06 ,  G06F13/00

CPC分类号： G06F5/065

摘要： In accordance with the present invention, there is provided a dual channel FIFO circuit to perform bidirectional data transfer under the control of a host computer between a host interface and a small computer system interface, comprising: a first multiplexing means for selecting one of the data from said host interface and the data from said small computer system interface; a single ported SRAM for storing the selected data by said first multiplexing means and outputting the data, which are indicated by pointers, according to the requests from said host interface or said small computer system interface; a second multiplexing means for selecting one of the data from said single ported SRAM and the data from said small computer system interface; a first staging memory means for storing the data to be outputted to said host interface; and a second staging memory means for storing the selected data by said second multiplexing means and transferring them to said second multiplexing means and said small computer system interface.

摘要翻译： 根据本发明，提供了一种双通道FIFO电路，用于在主机接口和小型计算机系统接口之间的主计算机的控制下执行双向数据传输，包括：第一多路复用装置，用于选择一个数据 从所述主机接口和来自所述小型计算机系统接口的数据; 单端口SRAM，用于存储所述第一复用装置所选择的数据，并根据来自所述主机接口或所述小型计算机系统接口的请求，输出由指针指示的数据; 第二复用装置，用于从所述单端口SRAM中选择一个数据和来自所述小型计算机系统接口的数据; 第一分段存储装置，用于存储要输出到所述主机接口的数据; 以及第二分段存储装置，用于通过所述第二多路复用装置存储所选择的数据并将其传送到所述第二多路复用装置和所述小型计算机系统接口。

公开(公告)号：US20120254998A1

公开(公告)日：2012-10-04

申请号：US13394112

申请日：2010-07-29

申请人： Jae Hwang Lee ,  Young Hwan Kim ,  Dong Woo Shin

发明人： Jae Hwang Lee ,  Young Hwan Kim ,  Dong Woo Shin

IPC分类号： G06F21/00

CPC分类号： G06F21/51

摘要： The present invention discloses a method of blocking the execution of a hacking process. In the method, a security process selects a process to be tested. The security process extracts the pattern of the process to be tested and compares it with hack diagnosis references. If the pattern of the process to be tested is included in the hack diagnosis references, the security process determines that the process to be tested is a hacking process. The security process calculates the unique hash value of the hacking process and compares it with hack blocking references. If the unique hash value of the hacking process is included in the hack blocking references, the security process blocks the execution of the hacking process, and, if the unique hash value of the hacking process is not included in the hack blocking references, the security process does not block the execution of the hacking process.

摘要翻译： 本发明公开了一种阻止黑客进程执行的方法。 在该方法中，安全过程选择要测试的过程。 安全过程提取要测试过程的模式，并将其与黑客诊断参考进行比较。 如果被测试过程的模式包含在黑客诊断参考中，则安全过程确定要测试的过程是一个黑客进程。 安全过程计算黑客进程的唯一哈希值，并将其与黑客阻塞引用进行比较。 如果黑客入侵进程的唯一哈希值包含在黑客拦截引用中，则安全过程将阻止黑客进程的执行，并且如果黑客攻击进程的唯一哈希值不包括在黑客拦截引用中，则安全性 进程不会阻止黑客进程的执行。

公开(公告)号：US06822920B2

公开(公告)日：2004-11-23

申请号：US10639922

申请日：2003-08-12

申请人： In Sun Yoo ,  Sun Hyoung Lee ,  Dong Woo Shin

发明人： In Sun Yoo ,  Sun Hyoung Lee ,  Dong Woo Shin

IPC分类号： G11C700

CPC分类号： G11C11/40615 ,  G11C11/406 ,  G11C2211/4061

摘要： Disclosed herein is a synchronous SRAM-compatible memory using DRAM cells. In the synchronous SRAM-compatible memory of the present invention, a refresh operation is controlled in response to a refresh clock signal having a period “n” times a period of a reference clock signal. The refresh operation is performed while a chip enable signal/CS is inactivated. A writing/reading access operation is performed in response to a writing/reading command generated while the chip enable signal/CS is activated. Therefore, in the writing/reading access operation of the synchronous SRAM-compatible memory of the present invention, no delay of time occurs that would otherwise occur due to the refresh operation of the DRAM cells.

摘要翻译： 这里公开了使用DRAM单元的同步SRAM兼容存储器。 在本发明的同步SRAM兼容存储器中，响应于具有基准时钟信号的周期的周期“n”的刷新时钟信号来控制刷新操作。 在芯片使能信号/ CS被激活时执行刷新操作。 响应于在芯片使能信号/ CS被激活时产生的写入/读取命令执行写入/读取访问操作。 因此，在本发明的同步SRAM兼容存储器的写/读访问操作中，不会由于DRAM单元的刷新操作而发生时间延迟。

公开(公告)号：US06735669B2

公开(公告)日：2004-05-11

申请号：US09751395

申请日：2001-01-02

申请人： Dong Woo Shin

发明人： Dong Woo Shin

IPC分类号： G06F1200

CPC分类号： G06F1/3225 ,  G06F1/3203 ,  G06F1/3275 ,  G11C7/22 ,  G11C7/222 ,  G11C11/406 ,  G11C11/4076 ,  Y02D10/14

摘要： This Rambus DRAM has a power save function which is not restricted in using time and has a short setting time, by forcibly compensating for a lost capacitor value in a memory cell to have a predetermined value, when a power save mode is changed to a normal mode. The Rambus DRAM includes: a memory core unit having a plurality of memory cells and a refresh counter; a packet controller for analyzing a packet control signal applied from an external channel, and generating a control signal for controlling a power mode; a power mode controller for generating each power mode signal and a self refresh enable signal for controlling the operation of the refresh counter according to the control signal; and a delay locked loop controlled according to the power mode signals, for adjusting a phase difference between a clock signal applied from the external channel and a clock signal used in a semiconductor memory device, generating to the power mode controller a signal notifying that the mode can be changed to a normal mode, and compensating for a current value lost in a capacitor of the memory cell.

摘要翻译： 该Rambus DRAM具有省电功能，其在使用时间上不受限制，并且具有短的设置时间，通过强制地补偿存储器单元中的损耗电容器值以具有预定值，当节电模式改变为正常时 模式。 Rambus DRAM包括：具有多个存储单元和刷新计数器的存储器核心单元; 分组控制器，用于分析从外部信道施加的分组控制信号，并产生用于控制功率模式的控制信号; 功率模式控制器，用于产生每个功率模式信号;以及自刷新使能信号，用于根据控制信号控制刷新计数器的操作; 以及根据功率模式信号控制的延迟锁定环路，用于调整从外部信道施加的时钟信号与在半导体存储器件中使用的时钟信号之间的相位差，向功率模式控制器产生通知模式 可以改变到正常模式，并补偿在存储单元的电容器中损失的电流值。

公开(公告)号：US06709916B2

公开(公告)日：2004-03-23

申请号：US10330583

申请日：2002-12-27

申请人： Kwang Jun Cho ,  Ki Seon Park ,  Kyong Min Kim ,  Dong Woo Shin

发明人： Kwang Jun Cho ,  Ki Seon Park ,  Kyong Min Kim ,  Dong Woo Shin

IPC分类号： H01L218242

CPC分类号： H01L28/56 ,  C23C16/409 ,  H01L21/31691 ,  H01L27/10855

摘要： A method for forming a capacitor of a semiconductor device having a dielectric film of high dielectric constant having three-dimensional structure for securing capacitance of semiconductor device in order to have excellent deposition characteristics, by forming a storage electrode formed of Ru film on a semiconductor substrate and forming dielectric films formed of high dielectric constant materials having excellent step coverage on the surface of the storage electrode, the dielectric films having a stacked structure of a first dielectric film formed at low deposition speed and a second dielectric film formed at higher deposition speed by reducing the amount of added gas, thereby performing the subsequent process easily and improving yield and productivity of semiconductor device and then embodying high integration of semiconductor device.

摘要翻译： 一种用于形成半导体器件的电容器的方法，具有具有三维结构的具有三维结构的介电膜的半导体器件的电容器，用于通过在半导体衬底上形成由Ru膜形成的存储电极以便具有优异的淀积特性，从而确保半导体器件的电容 以及在所述存储电极的表面上形成由具有优异阶梯覆盖度的高介电常数材料形成的电介质膜，所述电介质膜具有以低沉积速度形成的第一电介质膜的堆叠结构和以较高沉积速度形成的第二电介质膜 减少添加气体的量，从而容易地进行后续处理，并提高半导体器件的产率和生产率，然后体现半导体器件的高集成度。

公开(公告)号：US06342801B1

公开(公告)日：2002-01-29

申请号：US09606281

申请日：2000-06-29

申请人： Dong Woo Shin

发明人： Dong Woo Shin

IPC分类号： H03K502

CPC分类号： G11C7/222 ,  G11C7/22 ,  H03K5/023 ,  H03K5/1565 ,  H03L7/0812

摘要： A duty cycle correction circuit of a delay locked loop circuit in a Rambus DRAM, decreasing a clock locking time by previously correcting a storage capacitor value to a setting value so as to provide a duty cycle correction within a short time in exiting a power save mode of delay locked loop, and accordingly, can realize a the power save mode capable of a high speed movement and without a time limit.

摘要翻译： 一种Rambus DRAM中的延迟锁定环电路的占空比校正电路，通过将存储电容器值预先校正为设定值来减小时钟锁定时间，从而在退出省电模式的短时间内提供占空比校正 的延迟锁定环路，从而能够实现能够高速运转且没有时间限制的省电模式。