公开(公告)号：US08802533B1

公开(公告)日：2014-08-12

申请号：US13989297

申请日：2012-07-30

Applicant: Changliang Qin ,  Huaxiang Yin

Inventor： Changliang Qin ,  Huaxiang Yin

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7833 ,  H01L29/1045 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A transistor device comprising epitaxial LDD and Halo regions and a method of manufacturing the same are disclosed. According to embodiments of the present disclosure, the method may comprise: forming a gate stack on a semiconductor substrate; forming a gate spacer which covers the top of the gate stack and sidewalls of the gate stack; forming source/drain grooves; epitaxially growing a Halo material layer in the source/drain grooves, wherein the Halo material layer has a first doping element therein; epitaxially growing source/drain regions which apply stress to a channel region of the device, wherein the source/drain regions have a second doping element, opposite in conductivity to the first doping element, therein; isotropically etching the source/drain regions to remove portions of the source/drain regions, wherein the etching also removes portions of the Halo material layer directly under the gate spacer and extends to the channel region to some extent, wherein remaining portions of the Halo material layer constitute Halo regions of the device; and epitaxially growing an LDD material layer to form LDD regions of the device.

Abstract translation: 公开了一种包括外延LDD和Halo区域的晶体管器件及其制造方法。 根据本公开的实施例，该方法可以包括：在半导体衬底上形成栅极堆叠; 形成覆盖栅极堆叠的顶部和栅极叠层的侧壁的栅极间隔物; 形成源极/漏极沟槽; 在源极/漏极沟槽中外延生长Halo材料层，其中Halo材料层在其中具有第一掺杂元素; 外延生长的源极/漏极区域，其对器件的沟道区域施加应力，其中源极/漏极区域具有与第一掺杂元件的导电性相反的第二掺杂元素; 各向同性蚀刻源/漏区以去除源极/漏极区的部分，其中蚀刻还将栅极间隔物正下方的Halo材料层的部分去除并在一定程度上延伸到沟道区，其中Halo材料的剩余部分 层构成设备的光晕区域; 并外延生长LDD材料层以形成器件的LDD区域。

公开(公告)号：US20140057404A1

公开(公告)日：2014-02-27

申请号：US13989164

申请日：2012-07-31

Applicant: Changliang Qin ,  Peizhen Hong ,  Huaxiang Yin

Inventor： Changliang Qin ,  Peizhen Hong ,  Huaxiang Yin

IPC: H01L21/306 ,  H01L29/66

CPC classification number: H01L21/30604 ,  H01L21/26506 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/66477 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device is disclosed. In one embodiment, the method comprises: forming a gate stack on a substrate; etching the substrate on both sides of the gate stack to form C-shaped source/drain grooves; and wet-etching the C-shaped source/drain grooves to form Σ-shaped source/drain grooves. With this method, it is possible to effectively increase stress applied to a channel region, to accurately control a depth of the source/drain grooves, and to reduce roughness of side walls and bottom portions of the grooves and thus reduce defects by etching the C-shaped source/drain grooves and then further wet-etching them to form the Σ-shaped source/drain grooves.

Abstract translation: 公开了制造半导体器件的方法。 在一个实施例中，该方法包括：在衬底上形成栅叠层; 在栅极堆叠的两侧蚀刻衬底以形成C形源极/漏极沟槽; 并对C形源极/漏极沟槽进行湿蚀刻以形成Σ型源极/漏极沟槽。 通过该方法，能够有效地增加施加于沟道区域的应力，精确地控制源极/漏极沟槽的深度，并且可以减小沟槽的侧壁和底部的粗糙度，从而通过蚀刻C来减少缺陷 形状的源极/漏极沟槽，然后进一步湿法蚀刻它们以形成Sigma形状的源极/漏极沟槽。

公开(公告)号：US20140217519A1

公开(公告)日：2014-08-07

申请号：US13989297

申请日：2012-07-30

Applicant: Changliang Qin ,  Huaxiang Yin

Inventor： Changliang Qin ,  Huaxiang Yin

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7833 ,  H01L29/1045 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A transistor device comprising epitaxial LDD and Halo regions and a method of manufacturing the same are disclosed. According to embodiments of the present disclosure, the method may comprise: forming a gate stack on a semiconductor substrate; forming a gate spacer which covers the top of the gate stack and sidewalls of the gate stack; forming source/drain grooves; epitaxially growing a Halo material layer in the source/drain grooves, wherein the Halo material layer has a first doping element therein; epitaxially growing source/drain regions which apply stress to a channel region of the device, wherein the source/drain regions have a second doping element, opposite in conductivity to the first doping element, therein; isotropically etching the source/drain regions to remove portions of the source/drain regions, wherein the etching also removes portions of the Halo material layer directly under the gate spacer and extends to the channel region to some extent, wherein remaining portions of the Halo material layer constitute Halo regions of the device; and epitaxially growing an LDD material layer to form LDD regions of the device.

Abstract translation: 公开了一种包括外延LDD和Halo区域的晶体管器件及其制造方法。 根据本公开的实施例，该方法可以包括：在半导体衬底上形成栅极堆叠; 形成覆盖栅极堆叠的顶部和栅极叠层的侧壁的栅极间隔物; 形成源极/漏极沟槽; 在源极/漏极沟槽中外延生长Halo材料层，其中Halo材料层在其中具有第一掺杂元素; 外延生长的源极/漏极区域，其对器件的沟道区域施加应力，其中源极/漏极区域具有与第一掺杂元件的导电性相反的第二掺杂元素; 各向同性蚀刻源/漏区以去除源极/漏极区的部分，其中蚀刻还将栅极间隔物正下方的Halo材料层的部分去除并在一定程度上延伸到沟道区，其中Halo材料的剩余部分 层构成设备的光晕区域; 并外延生长LDD材料层以形成器件的LDD区域。

公开(公告)号：US20140191335A1

公开(公告)日：2014-07-10

申请号：US13812941

申请日：2012-08-27

Applicant: Huaxiang Yin ,  Changliang Qin ,  Xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Changliang Qin ,  Xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/66818 ,  H01L29/7845 ,  H01L29/785

Abstract: The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located in the fins below the gate stack structures; characterized in that the stress layers have connected parts in the fins and that the channel regions enclose the connected parts.

Abstract translation: 本发明公开了一种半导体器件，包括位于基片上并沿着第一方向延伸的多个翅片; 多个栅极堆叠结构，沿着第二方向延伸并穿过每个所述散热片; 多个应力层，其位于所述栅极叠层结构的两侧的所述鳍片中，并且在其中具有多个源极和漏极区域; 多个通道区域，位于所述栅极叠层结构下方的鳍中; 其特征在于，应力层在翅片中具有连接部分，并且通道区域包围连接部分。

公开(公告)号：US08652891B1

公开(公告)日：2014-02-18

申请号：US13812867

申请日：2012-08-27

Applicant: Huaxiang Yin ,  Changliang Qin ,  Qiuxia Xu ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Changliang Qin ,  Qiuxia Xu ,  Dapeng Chen

IPC: H01L21/338

CPC classification number: H01L21/823431 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7853

Abstract: The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located between the plurality of source and drain regions along a first direction; characterized in that the plurality of gate stack structures enclose the plurality of channel regions. In accordance with the semiconductor device and the method of manufacturing the same of the present invention, an all-around nanowire metal multi-gate is formed in self-alignment by punching through and etching the fins at which the channel regions are located using a combination of the hard mask and the dummy gate, thus the device performance is enhanced.

Abstract translation: 本发明公开了一种半导体器件，包括位于基片上并沿着第一方向延伸的多个翅片; 多个栅极堆叠结构，沿着第二方向延伸并穿过每个所述散热片; 多个应力层，其位于所述栅极叠层结构的两侧的所述鳍片中，并且在其中具有多个源极和漏极区域; 沿着第一方向位于所述多个源区和漏区之间的多个沟道区; 其特征在于，所述多个栅极堆叠结构包围所述多个沟道区域。 根据本发明的半导体器件及其制造方法，通过使用组合来对通道区域所在的鳍进行冲压和蚀刻来形成全自动纳米线金属多栅极的自对准 的硬掩模和伪栅极，从而提高了器件性能。

公开(公告)号：US20130316509A1

公开(公告)日：2013-11-28

申请号：US13580962

申请日：2012-06-12

Applicant: Changliang Qin ,  Huaxiang Yin

Inventor： Changliang Qin ,  Huaxiang Yin

IPC: H01L21/336

CPC classification number: H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: The present invention provides a manufacturing method for a semiconductor device having epitaxial source/drain regions, in which a diffusion barrier layer of the source/drain regions made of epitaxial silicon-carbon or germanium silicon-carbon are added on the basis of epitaxially growing germanium-silicon of the source/drain regions in the prior art process, and the introduction of the diffusion barrier layer of the source/drain regions prevents diffusion of the dopant in the source/drain regions, thus mitigating the SCE and DIBL effect. The use of the diffusion barrier layer for the source/drain regions can also reduce the dosage of HALO implantation in the subsequent step, thus if HALO is performed before epitaxial growth of the source/drain regions, impact on the surfaces of the source/drain regions can be alleviated; if HALO is performed after epitaxial growth of the source/drain regions, the stress release effect of the epitaxial layer of the source drain/regions caused by the implantation can be reduced as much as possible.

Abstract translation: 本发明提供了一种具有外延源极/漏极区域的半导体器件的制造方法，其中基于外延生长锗添加由外延硅 - 碳或锗硅 - 碳制成的源极/漏极区的扩散阻挡层 在现有技术的工艺中源极/漏极区域的硅，以及源极/漏极区域的扩散阻挡层的引入防止了掺杂剂在源/漏区域中的扩散，从而减轻了SCE和DIBL效应。 用于源极/漏极区域的扩散阻挡层的使用也可以降低后续步骤中的HALO注入的剂量，因此如果在源极/漏极区域的外延生长之前执行HALO，则冲击源极/漏极 地区可以缓解; 如果在源/漏区的外延生长之后执行HALO，则可以尽可能地减少由注入引起的源漏极/区域的外延层的应力释放效应。

公开(公告)号：US20130256664A1

公开(公告)日：2013-10-03

申请号：US13519884

申请日：2012-04-10

Applicant: Changliang Qin ,  Huaxiang Yin

Inventor： Changliang Qin ,  Huaxiang Yin

IPC: H01L29/10 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: This invention relates to a MOS device for making the source/drain region closer to the channel region and a method of manufacturing the same, comprising: providing an initial structure, which includes a substrate, an active region, and a gate stack; performing ion implantation in the active region on both sides of the gate stack, such that part of the substrate material undergoes pre-amorphization to form an amorphous material layer; forming a first spacer; with the first spacer as a mask, performing dry etching, thereby forming a recess, with the amorphous material layer below the first spacer kept; performing wet etching using an etchant solution that is isotropic to the amorphous material layer and whose etch rate to the amorphous material layer is greater than or substantially equal to the etch rate to the {100} and {110} surfaces of the substrate material but is far greater than the etch rate to the {111} surface of the substrate material, thus removing the amorphous material layer below the first spacer, such that the substrate material below the amorphous material layer is exposed to the solution and is etched thereby, and in the end, forming a Sigma shaped recess that extends to the nearby region below the gate stack; and epitaxially forming SiGe in the Sigma shaped recess.

Abstract translation: 本发明涉及一种用于使源极/漏极区域更靠近沟道区域的MOS器件及其制造方法，包括：提供包括衬底，有源区域和栅极堆叠的初始结构; 在栅极堆叠的两侧上的有源区中进行离子注入，使得衬底材料的一部分经历预非晶化以形成无定形材料层; 形成第一间隔物; 以第一间隔物作为掩模，进行干蚀刻，从而形成凹部，保持第一间隔物下面的非晶材料层; 使用对非晶材料层各向同性的蚀刻剂溶液进行湿蚀刻，并且其对非晶材料层的蚀刻速率大于或基本上等于对基板材料的{100}和{110}表面的蚀刻速率，但是 远远大于衬底材料的{111}表面的蚀刻速率，从而去除第一间隔物下方的无定形材料层，使得无定形材料层下面的衬底材料暴露于溶液并被蚀刻，并且在 结束，形成延伸到栅堆叠下方的附近区域的Sigma形凹部; 并在Sigma形凹部中外延形成SiGe。

公开(公告)号：US20150102416A1

公开(公告)日：2015-04-16

申请号：US14396845

申请日：2012-05-17

Applicant: Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Dapeng Chen

IPC: H01L21/8234 ,  H01L29/51 ,  H01L27/092

CPC classification number: H01L21/28088 ,  H01L21/28 ,  H01L21/28008 ,  H01L21/28026 ,  H01L21/28044 ,  H01L21/28079 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/517 ,  H01L29/66515 ,  H01L29/66545

Abstract: A method for manufacturing a dual metal CMOS device comprising: forming a first type metal work function modulation layer in the first gate trench and the second gate trench; forming a second type work function metal diffusion source layer in the first gate trench and the second gate trench; forming a heat isolation layer that shields the region of the first type device; and thermally annealing the regions where the first type device and the second type device are located.

Abstract translation: 一种用于制造双金属CMOS器件的方法，包括：在所述第一栅极沟槽和所述第二栅极沟槽中形成第一类型金属功函数调制层; 在所述第一栅极沟槽和所述第二栅极沟槽中形成第二类型功函数金属扩散源层; 形成屏蔽所述第一类型装置的区域的热隔离层; 并对第一类型器件和第二类型器件所在的区域进行热退火。

公开(公告)号：US08994119B2

公开(公告)日：2015-03-31

申请号：US13520618

申请日：2012-04-11

Applicant: Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

IPC: H01L27/088 ,  H01L21/8236 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L21/823807 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7845

Abstract: The present invention discloses a semiconductor device, comprising substrates, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer; Each of the second gate stack structures comprises a second gate insulating layer, a first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the first work function metal layer has a first stress, and the gate filling layer has a second stress. Two metal gate layers of different types and/or intensity of stress are formed, respectively, thus different stresses are applied to the channel regions of different MOSFETs effectively and accurately, the device carrier mobility is enhanced simply and efficiently, and the device performance is also enhanced.

Abstract translation: 本发明公开了一种半导体器件，包括衬底，衬底上的多个栅极堆叠结构，在每个栅极堆叠结构的两侧上的多个栅极间隔结构，在衬底的两侧的多个源极和漏极区域 每个栅极间隔结构，所述多个栅极间隔结构包括多个第一栅极堆叠结构和多个第二栅极堆叠结构，其中所述第一栅极堆叠结构中的每一个包括第一栅极绝缘层，第一功函数金属层， 第二功函数金属扩散阻挡层和栅极填充层; 每个第二栅极堆叠结构包括第二栅极绝缘层，第一功函数金属层，第二功函数金属层和栅极填充层，其特征在于，第一功函数金属层具有第一应力，并且 栅极填充层具有第二应力。 形成不同类型和/或应力强度的两个金属栅极层，从而有效且准确地对不同MOSFET的沟道区域施加不同的应力，简化高效地提高器件载流子迁移率，器件性能也 增强。

公开(公告)号：US08816326B2

公开(公告)日：2014-08-26

申请号：US13497249

申请日：2011-11-25

Applicant: Huaxiang Yin ,  Jun Luo ,  Chao Zhao ,  Honggang Liu ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Jun Luo ,  Chao Zhao ,  Honggang Liu ,  Dapeng Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/778 ,  H01L29/08

CPC classification number: H01L29/66462 ,  H01L29/0895 ,  H01L29/7391 ,  H01L29/7785 ,  Y10S977/938

Abstract: A semiconductor device, which comprises: a semiconductor substrate; a channel region on the semiconductor substrate, said channel region including a quantum well structure; a source region and a drain region on the sides of the channel region; a gate structure on the channel region; wherein the materials for the channel region, the source region and the drain region have different energy bands, and a tunneling barrier structure exists between the source region and the channel region.

Abstract translation: 一种半导体器件，包括：半导体衬底; 半导体衬底上的沟道区，所述沟道区包括量子阱结构; 在沟道区域的侧面上的源极区域和漏极区域; 通道区域上的栅极结构; 其中用于沟道区，源区和漏区的材料具有不同的能带，并且在源极区域和沟道区域之间存在隧道势垒结构。