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    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20130241004A1

    公开(公告)日：2013-09-19

    申请号：US13520618

    申请日：2012-04-11

    Applicant: Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

    Inventor： Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

    IPC: H01L27/088 ,  H01L21/8236

    CPC classification number: H01L21/823807 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7845

    Abstract: The present invention discloses a semiconductor device, comprising substrates, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer; Each of the second gate stack structures comprises a second gate insulating layer, a first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the first work function metal layer has a first stress, and the gate filling layer has a second stress. Two metal gate layers of different types and/or intensity of stress are formed, respectively, thus different stresses are applied to the channel regions of different MOSFETs effectively and accurately, the device carrier mobility is enhanced simply and efficiently, and the device performance is also enhanced.

    Abstract translation: 本发明公开了一种半导体器件，包括衬底，衬底上的多个栅极堆叠结构，在每个栅极堆叠结构的两侧上的多个栅极间隔结构，在衬底的两侧的多个源极和漏极区域 每个栅极间隔结构，所述多个栅极间隔结构包括多个第一栅极堆叠结构和多个第二栅极堆叠结构，其中所述第一栅极堆叠结构中的每一个包括第一栅极绝缘层，第一功函数金属层， 第二功函数金属扩散阻挡层和栅极填充层; 每个第二栅极堆叠结构包括第二栅极绝缘层，第一功函数金属层，第二功函数金属层和栅极填充层，其特征在于，第一功函数金属层具有第一应力，并且 栅极填充层具有第二应力。 形成不同类型和/或应力强度的两个金属栅极层，从而有效且准确地对不同MOSFET的沟道区域施加不同的应力，简单高效地提高器件载流子迁移率，器件性能也是 增强。

    Semiconductor device with gate stacks having stress and method of manufacturing the same
    4.
    发明授权
    Semiconductor device with gate stacks having stress and method of manufacturing the same 有权
    具有应力的栅极堆叠的半导体器件及其制造方法

    公开(公告)号：US08994119B2

    公开(公告)日：2015-03-31

    申请号：US13520618

    申请日：2012-04-11

    Applicant: Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

    Inventor： Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

    IPC: H01L27/088 ,  H01L21/8236 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/51 ,  H01L29/66

    CPC classification number: H01L21/823807 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7845

    Abstract: The present invention discloses a semiconductor device, comprising substrates, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer; Each of the second gate stack structures comprises a second gate insulating layer, a first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the first work function metal layer has a first stress, and the gate filling layer has a second stress. Two metal gate layers of different types and/or intensity of stress are formed, respectively, thus different stresses are applied to the channel regions of different MOSFETs effectively and accurately, the device carrier mobility is enhanced simply and efficiently, and the device performance is also enhanced.

    Abstract translation: 本发明公开了一种半导体器件，包括衬底，衬底上的多个栅极堆叠结构，在每个栅极堆叠结构的两侧上的多个栅极间隔结构，在衬底的两侧的多个源极和漏极区域 每个栅极间隔结构，所述多个栅极间隔结构包括多个第一栅极堆叠结构和多个第二栅极堆叠结构，其中所述第一栅极堆叠结构中的每一个包括第一栅极绝缘层，第一功函数金属层， 第二功函数金属扩散阻挡层和栅极填充层; 每个第二栅极堆叠结构包括第二栅极绝缘层，第一功函数金属层，第二功函数金属层和栅极填充层，其特征在于，第一功函数金属层具有第一应力，并且 栅极填充层具有第二应力。 形成不同类型和/或应力强度的两个金属栅极层，从而有效且准确地对不同MOSFET的沟道区域施加不同的应力，简化高效地提高器件载流子迁移率，器件性能也 增强。

    SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    5.
    发明申请
    SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    半导体结构及其制造方法

    公开(公告)号：US20140231923A1

    公开(公告)日：2014-08-21

    申请号：US14346537

    申请日：2012-05-16

    Applicant: Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

    Inventor： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

    IPC: H01L27/092 ,  H01L21/8238

    CPC classification number: H01L27/092 ,  H01L21/76232 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7846 ,  H01L29/7848

    Abstract: The present invention provides a semiconductor structure, comprising: a substrate; a gate stack located on the substrate and comprising at least a gate dielectric layer and a gate electrode layer; source/drain regions, located in the substrate on both sides of the gate stack; an STI structure, located in the substrate on both sides of the source/drain regions, wherein the cross-section of the STI structure is trapezoidal, Sigma-shaped or inverted trapezoidal depending on the type of the semiconductor structure. Correspondingly, the present invention further to provides a method of manufacturing the semiconductor structure. In the present invention, STI structures having different shapes can be combined with different stress fillers to apply tensile stress or compressive stress laterally to the channel, which will produce a positive impact on the electron mobility of NMOS and the hole mobility of PMOS and increase the channel current of the device, thereby effectively improving the performance of the semiconductor structure.

    Abstract translation: 本发明提供一种半导体结构，包括：基板; 位于所述基板上并且至少包括栅极电介质层和栅极电极层的栅极堆叠; 源极/漏极区域，位于栅极堆叠两侧的衬底中; STI结构，位于源极/漏极区两侧的衬底中，其中根据半导体结构的类型，STI结构的横截面为梯形，Σ形或倒梯形。 相应地，本发明还提供一种制造半导体结构的方法。 在本发明中，具有不同形状的STI结构可以与不同的应力填料组合以向沟道侧向施加拉伸应力或压应力，这将对NMOS的电子迁移率和PMOS的空穴迁移率产生积极影响，并增加 通道电流，从而有效地提高了半导体结构的性能。

    Semiconductor structure and method for manufacturing the same
    6.
    发明授权
    Semiconductor structure and method for manufacturing the same 有权
    半导体结构及其制造方法

    公开(公告)号：US09276085B2

    公开(公告)日：2016-03-01

    申请号：US14387143

    申请日：2012-04-26

    Applicant: Huaxiang Yin ,  Xiaolong Ma ,  Changliang Qi ,  Qiuxia Xu ,  Dapeng Chen

    Inventor： Huaxiang Yin ,  Xiaolong Ma ,  Changliang Qi ,  Qiuxia Xu ,  Dapeng Chen

    IPC: H01L21/02 ,  H01L21/332 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/66575 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833

    Abstract: The present invention provides a semiconductor structure comprising a substrate; a gate stack on the substrate; a spacer on the sidewalls of the gate stack; a source/drain junction extension formed in the substrate on both sides of the gate stack by epitaxial growth; and a source/drain region in the substrate on both sides of the source/drain junction extension. Accordingly, the present invention also provides methods for manufacturing the semiconductor structure. The present invention can provide a source/drain junction extension with a high doping concentration and a low junction depth, thereby effectively improving the performance of the semiconductor structure.

    Abstract translation: 本发明提供一种包括基板的半导体结构; 衬底上的栅极堆叠; 在栅极堆叠的侧壁上的间隔物; 通过外延生长形成在栅极堆叠的两侧的衬底中的源极/漏极结延伸; 以及在源极/漏极结延伸部的两侧上的衬底中的源极/漏极区域。 因此，本发明还提供了制造半导体结构的方法。 本发明可以提供具有高掺杂浓度和低结深度的源极/漏极结延伸，从而有效地改善了半导体结构的性能。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20140191335A1

    公开(公告)日：2014-07-10

    申请号：US13812941

    申请日：2012-08-27

    Applicant: Huaxiang Yin ,  Changliang Qin ,  Xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

    Inventor： Huaxiang Yin ,  Changliang Qin ,  Xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

    IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088

    CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/66818 ,  H01L29/7845 ,  H01L29/785

    Abstract: The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located in the fins below the gate stack structures; characterized in that the stress layers have connected parts in the fins and that the channel regions enclose the connected parts.

    Abstract translation: 本发明公开了一种半导体器件，包括位于基片上并沿着第一方向延伸的多个翅片; 多个栅极堆叠结构，沿着第二方向延伸并穿过每个所述散热片; 多个应力层，其位于所述栅极叠层结构的两侧的所述鳍片中，并且在其中具有多个源极和漏极区域; 多个通道区域，位于所述栅极叠层结构下方的鳍中; 其特征在于，应力层在翅片中具有连接部分，并且通道区域包围连接部分。

    Semiconductor device and method of manufacturing the same
    9.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08652891B1

    公开(公告)日：2014-02-18

    申请号：US13812867

    申请日：2012-08-27

    Applicant: Huaxiang Yin ,  Changliang Qin ,  Qiuxia Xu ,  Dapeng Chen

    Inventor： Huaxiang Yin ,  Changliang Qin ,  Qiuxia Xu ,  Dapeng Chen

    IPC: H01L21/338

    CPC classification number: H01L21/823431 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7853

    Abstract: The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located between the plurality of source and drain regions along a first direction; characterized in that the plurality of gate stack structures enclose the plurality of channel regions. In accordance with the semiconductor device and the method of manufacturing the same of the present invention, an all-around nanowire metal multi-gate is formed in self-alignment by punching through and etching the fins at which the channel regions are located using a combination of the hard mask and the dummy gate, thus the device performance is enhanced.

    Abstract translation: 本发明公开了一种半导体器件，包括位于基片上并沿着第一方向延伸的多个翅片; 多个栅极堆叠结构，沿着第二方向延伸并穿过每个所述散热片; 多个应力层，其位于所述栅极叠层结构的两侧的所述鳍片中，并且在其中具有多个源极和漏极区域; 沿着第一方向位于所述多个源区和漏区之间的多个沟道区; 其特征在于，所述多个栅极堆叠结构包围所述多个沟道区域。 根据本发明的半导体器件及其制造方法，通过使用组合来对通道区域所在的鳍进行冲压和蚀刻来形成全自动纳米线金属多栅极的自对准 的硬掩模和伪栅极，从而提高了器件性能。

    Semiconductor Device and Method of Manufacturing the Same
    10.
    发明申请
    Semiconductor Device and Method of Manufacturing the Same 有权
    半导体器件及其制造方法

    公开(公告)号：US20130256808A1

    公开(公告)日：2013-10-03

    申请号：US13520791

    申请日：2012-04-11

    Applicant: Huaxiang Yin ,  xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

    Inventor： Huaxiang Yin ,  xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

    IPC: H01L27/088 ,  H01L21/8236

    CPC classification number: H01L21/823807 ,  H01L29/7833 ,  H01L29/7843

    Abstract: The present invention discloses a semiconductor device, comprising a first MOSFET; a second MOSFET; a first stress liner covering the first MOSFET and having a first stress; a second stress liner covering the second MOSFET and having a second stress; wherein the second stress liner and/or the first stress liner comprise(s) a metal oxide. In accordance with the high-stress CMOS and method of manufacturing the same of the present invention, a stress layer comprising a metal oxide is formed selectively on PMOS and NMOS respectively by using a CMOS compatible process, whereby carrier mobility of the channel region is effectively enhanced and the performance of the device is improved.

    Abstract translation: 本发明公开了一种半导体器件，包括第一MOSFET; 第二个MOSFET; 覆盖所述第一MOSFET并具有第一应力的第一应力衬垫; 覆盖所述第二MOSFET并具有第二应力的第二应力衬垫; 其中所述第二应力衬垫和/或所述第一应力衬垫包括金属氧化物。 根据本发明的高应力CMOS及其制造方法，通过使用CMOS兼容工艺，分别在PMOS和NMOS上选择性地形成包含金属氧化物的应力层，由此，沟道区域的载流子迁移率有效地 增强了设备的性能，提高了设备​​性能。

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