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187 条记录 (耗时 0.03 秒)

    Photo alignment mark for a gate last process
    14.
    发明授权
    Photo alignment mark for a gate last process 有权
    最后一个进程的照片对齐标记

    公开(公告)号：US08598630B2

    公开(公告)日：2013-12-03

    申请号：US12470333

    申请日：2009-05-21

    申请人： Gary Shen ,  Ming-Yuan Wu ,  Chiung-Han Yeh ,  Kong-Beng Thei ,  Harry Chuang

    发明人： Gary Shen ,  Ming-Yuan Wu ,  Chiung-Han Yeh ,  Kong-Beng Thei ,  Harry Chuang

    IPC分类号： H01L23/52

    CPC分类号： H01L23/544 ,  H01L21/31051 ,  H01L21/823828 ,  H01L23/585 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device is provided which includes a semiconductor substrate having a first region and a second region, the first and second regions being isolated from each other, a plurality of transistors formed in the first region, an alignment mark formed in the second region, the alignment mark having a plurality of active regions in a first direction, and a dummy gate structure formed over the alignment mark, the dummy gate structure having a plurality of lines in a second direction different from the first direction.

    摘要翻译： 提供一种半导体器件，其包括具有第一区域和第二区域的半导体衬底，第一和第二区域彼此隔离，形成在第一区域中的多个晶体管，形成在第二区域中的对准标记， 对准标记具有在第一方向上的多个有效区域，以及形成在所述对准标记上的伪栅极结构，所述伪栅极结构在与所述第一方向不同的第二方向上具有多条线。

    Dishing-free gap-filling with multiple CMPs
    15.
    发明授权
    Dishing-free gap-filling with multiple CMPs 有权

    公开(公告)号：US08552522B2

    公开(公告)日：2013-10-08

    申请号：US13151666

    申请日：2011-06-02

    申请人： Ming-Yuan Wu ,  Kong-Beng Thei ,  Chiung-Han Yeh ,  Harry Chuang ,  Mong-Song Liang

    发明人： Ming-Yuan Wu ,  Kong-Beng Thei ,  Chiung-Han Yeh ,  Harry Chuang ,  Mong-Song Liang

    IPC分类号： H01L21/70

    CPC分类号： H01L21/76883 ,  H01L21/76229

    摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.

    METAL GATE SEMICONDUCTOR DEVICE
    20.
    发明申请
    METAL GATE SEMICONDUCTOR DEVICE 有权
    金属栅极半导体器件

    公开(公告)号：US20120012948A1

    公开(公告)日：2012-01-19

    申请号：US13245494

    申请日：2011-09-26

    申请人： Ching-Han Yeh ,  Chen-Pin Hsu ,  Ming-Yuan Wu ,  Kong-Beng Thei ,  Harry Chuang

    发明人： Ching-Han Yeh ,  Chen-Pin Hsu ,  Ming-Yuan Wu ,  Kong-Beng Thei ,  Harry Chuang

    IPC分类号： H01L29/78

    CPC分类号： H01L29/42376 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28105 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

    摘要： A semiconductor device includes a semiconductor substrate, a source and a drain region formed on the semiconductor substrate, and a gate structure disposed on the substrate between the source and drain regions. The gate structure includes an interfacial layer formed over the substrate, a high-k dielectric formed over the interfacial layer, and a metal gate formed over the high-k dielectric that includes a first metal layer and a second metal layer, where the first metal layer is formed on a portion of the sidewalls of the gate structure and where the second metal layer is formed on another portion of the sidewalls of the gate structure.

    摘要翻译： 半导体器件包括半导体衬底，形成在半导体衬底上的源极和漏极区域以及设置在源极和漏极区域之间的衬底上的栅极结构。 栅极结构包括在衬底上形成的界面层，在界面层上形成的高k电介质，以及形成在包括第一金属层和第二金属层的高k电介质上的金属栅，其中第一金属 层形成在栅极结构的侧壁的一部分上，并且第二金属层形成在栅极结构的侧壁的另一部分上。