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公开(公告)号：US20110307666A1
公开(公告)日：2011-12-15
申请号：US13159590
申请日：2011-06-14
IPC分类号： G06F12/12
CPC分类号： G06F12/0897 , G06F12/12 , G06F2212/507
摘要： Data caching for use in a computer system including a lower cache memory and a higher cache memory. The higher cache memory receives a fetch request. It is then determined by the higher cache memory the state of the entry to be replaced next. If the state of the entry to be replaced next indicates that the entry is exclusively owned or modified, the state of the entry to be replaced next is changed such that a following cache access is processed at a higher speed compared to an access processed if the state would stay unchanged.
摘要翻译： 数据缓存用于包括较低级高速缓冲存储器和较高级缓存的计算机系统。 较高的缓存存储器接收提取请求。 然后由更高的缓存存储器确定要被替换的条目的状态。 如果接下来被替换的条目的状态指示该条目是专门拥有或修改的，则下一个被替换的条目的状态被改变，使得如果处理的访问与处理的访问相比，以更高的速度处理以下高速缓存访问 国家将保持不变。
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公开(公告)号：US09411599B2
公开(公告)日：2016-08-09
申请号：US12822379
申请日：2010-06-24
申请人： Christian Jacobi , Barry W. Krumm , Brian R. Prasky , Martin Recktenwald , Chung-Lung K. Shum , Charles F. Webb , Joshua M. Weinberg
发明人： Christian Jacobi , Barry W. Krumm , Brian R. Prasky , Martin Recktenwald , Chung-Lung K. Shum , Charles F. Webb , Joshua M. Weinberg
CPC分类号： G06F9/3824 , G06F9/30043 , G06F9/3806 , G06F9/3844 , G06F9/3857
摘要： Data operand fetching control includes a computer processor that includes a control unit for determining memory access operations. The control unit is configured to perform a method. The method includes calculating a summation weight value for each instruction in a pipeline, the summation weight value calculated as a function of branch uncertainty and a pendency in which the instruction resides in the pipeline relative to other instructions in the pipeline. The method also includes mapping the summation weight value of a selected instruction that is attempting to access system memory to a memory access control, each memory access control specifying a manner of handling data fetching operations. The method further includes performing a memory access operation for the selected instruction based upon the mapping.
摘要翻译： 数据操作数获取控制包括计算机处理器，其包括用于确定存储器存取操作的控制单元。 控制单元被配置为执行方法。 该方法包括：计算流水线中每个指令的求和权重值，求和作为分支不确定度的函数计算的求和权重值以及相对于流水线中的其他指令，指令驻留在流水线中的挂起。 该方法还包括将尝试访问系统存储器的所选指令的求和权重值映射到存储器访问控制，每个存储器访问控制指定处理数据获取操作的方式。 该方法还包括基于映射执行针对所选择的指令的存储器访问操作。
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公开(公告)号：US20110320774A1
公开(公告)日：2011-12-29
申请号：US12822379
申请日：2010-06-24
申请人： Christian Jacobi , Barry W. Krumm , Brian R. Prasky , Martin Recktenwald , Chung-Lung K. Shum , Charles F. Webb , Joshua M. Weinberg
发明人： Christian Jacobi , Barry W. Krumm , Brian R. Prasky , Martin Recktenwald , Chung-Lung K. Shum , Charles F. Webb , Joshua M. Weinberg
IPC分类号： G06F9/38
CPC分类号： G06F9/3824 , G06F9/30043 , G06F9/3806 , G06F9/3844 , G06F9/3857
摘要： A system for data operand fetching control includes a computer processor that includes a control unit for determining memory access operations. The control unit is configured to perform a method. The method includes calculating a summation weight value for each instruction in a pipeline, the summation weight value calculated as a function of branch uncertainty and a pendency in which the instruction resides in the pipeline relative to other instructions in the pipeline. The method also includes mapping the summation weight value of a selected instruction that is attempting to access system memory to a memory access control, each memory access control specifying a manner of handling data fetching operations. The method further includes performing a memory access operation for the selected instruction based upon the mapping.
摘要翻译： 一种用于数据操作数取出控制的系统包括一计算机处理器，该计算机处理器包括用于确定存储器访问操作的控制 控制单元被配置为执行方法。 该方法包括：计算流水线中每个指令的求和权重值，求和作为分支不确定度的函数计算的求和权重值以及相对于流水线中的其他指令，指令驻留在流水线中的挂起。 该方法还包括将尝试访问系统存储器的所选择的指令的求和权重值映射到存储器访问控制，每个存储器访问控制指定处理数据获取操作的方式。 该方法还包括基于映射执行针对所选择的指令的存储器访问操作。
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14.发明授权Method, system and computer program product for an even sampling spread over differing clock domain boundaries 失效方法，系统和计算机程序产品，用于在不同的时钟域边界上进行均匀采样公开(公告)号：US07983372B2
公开(公告)日：2011-07-19
申请号：US12031158
申请日：2008-02-14
IPC分类号： H04L7/00
CPC分类号： H04L7/0008
摘要： The present invention relates to a method, computer program product and system for generating a sample signal from differing clock domain boundaries. The system comprises a cycle base component, a sample offset component being configured to receive a time-based sample pulse signal, and logic to generate a sample pulse. The sample pulse generation logic is configured to receive a time-based sample pulse signal, a free running counter value, a sample offset counter value, and deliver a sample pulse signal.
摘要翻译： 本发明涉及一种用于从不同时钟域边界产生采样信号的方法，计算机程序产品和系统。 该系统包括循环基础组件，被配置为接收基于时间的采样脉冲信号的采样偏移分量和用于产生采样脉冲的逻辑。 采样脉冲发生逻辑被配置为接收基于时间的采样脉冲信号，自由运行计数器值，采样偏移计数器值，并且传送采样脉冲信号。
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公开(公告)号：US07865749B2
公开(公告)日：2011-01-04
申请号：US10595520
申请日：2003-10-31
IPC分类号： G06F1/32
摘要： A method and apparatus for changing a clock frequency in a system (10) comprising a plurality of synchronous integrated circuit chips (12, 14, 16), and a circuit (20) for implementing the frequency change. The method includes: detecting a change in processing requirements in one of the plurality of synchronous integrated circuit chips; notifying the plurality of synchronous integrated circuit chips that a clock frequency change is to occur; achieving a quiescent bus state in each of the plurality of synchronous integrated circuit chips; notifying the plurality of synchronous integrated circuit chips that the clock frequency change can occur; and changing the clock frequency of the plurality of integrated circuit chips.
摘要翻译： 一种用于改变包括多个同步集成电路芯片（12,14,16）的系统（10）中的时钟频率的方法和装置，以及用于实现频率变化的电路（20）。 该方法包括：检测多个同步集成电路芯片之一中处理要求的变化; 通知多个同步集成电路芯片发生时钟频率变化; 在所述多个同步集成电路芯片的每一个中实现静态总线状态; 通知多个同步集成电路芯片可能发生时钟频率变化; 以及改变多个集成电路芯片的时钟频率。
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16.发明授权Providing accurate time-based counters for scaling operating frequencies of microprocessors 失效提供精确的时间计数器来缩放微处理器的工作频率公开(公告)号：US07602874B2
公开(公告)日：2009-10-13
申请号：US11340449
申请日：2006-01-26
申请人： Rolf Hilgendorf , Jens Kuenzer , Cedric Lichtenau , Thomas Pflueger , Martin Recktenwald , Andreas Schmid
发明人： Rolf Hilgendorf , Jens Kuenzer , Cedric Lichtenau , Thomas Pflueger , Martin Recktenwald , Andreas Schmid
IPC分类号： H04L7/00
摘要： A mechanism provides accurate time-based counters for scaling operating frequencies of microprocessors. The mechanism makes use of a time-based counter circuit configuration in which a fixed frequency clock is derived from a PLL of the clock generation circuit of the microprocessor and is used to feed the external and internal timebase logic as well as a timebase accumulator counter. The timebase accumulator counter accumulates the tick events from the timebase logic between two core clocks. The accumulated value is transferred to the core clock domain on every clock edge of a scalable clock and the accumulator is then reset. Because the accumulated ticks are transferred to the core clock domain before the accumulator is reset, no ticks are ever lost using the circuitry of the illustrative embodiment.
摘要翻译： 一种机制提供了精确的基于时间的计数器来缩放微处理器的工作频率。 该机制利用基于时间的计数器电路配置，其中从微处理器的时钟产生电路的PLL导出固定频率时钟，并且用于馈送外部和内部时基逻辑以及时基累加器计数器。 时基累加器计数器从两个核心时钟之间的时基逻辑累加tick事件。 累加值在可伸缩时钟的每个时钟沿传输到核心时钟域，然后累加器复位。 因为在累加器复位之前累积的刻度被传送到核心时钟域，所以使用说明性实施例的电路不会丢失任何刻度。
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17.发明申请MICROARCHITECTURE, METHOD AND COMPUTER PROGRAM PRODUCT FOR EFFICIENT DATA GATHERING FROM A SET OF TRACE ARRAYS 失效微观研究，方法和计算机程序产品，用于从一组跟踪阵列高效数据收集公开(公告)号：US20090217012A1
公开(公告)日：2009-08-27
申请号：US12036540
申请日：2008-02-25
申请人： Patrick M. West, JR. , Jane H. Bartik , Martin Recktenwald , Chung-Lung K. Shum , Scott B. Swaney
发明人： Patrick M. West, JR. , Jane H. Bartik , Martin Recktenwald , Chung-Lung K. Shum , Scott B. Swaney
IPC分类号： G06F9/22
CPC分类号： G06F11/3466
摘要： An architecture for collecting performance data in a processor, that includes: a trace read control unit and a trace data collect unit, each unit coupled to a plurality of trace array and multiplex units for providing performance data, the coupling accomplished by a trace read control bus, a data select bus, a trace row address bus and a data return bus; wherein each of the trace array and multiplex units receives a trace read signal and provides data including trace data and the trace read signal to the trace data collect unit. A method and a computer program product are provided.
摘要翻译： 一种用于在处理器中收集性能数据的架构，其包括：跟踪读取控制单元和跟踪数据收集单元，每个单元耦合到多个跟踪阵列和用于提供性能数据的多路复用单元，所述耦合由跟踪读取控制 总线，数据选择总线，跟踪行地址总线和数据返回总线; 其中每个跟踪阵列和多路复用单元接收跟踪读取信号，并将跟踪数据和跟踪读取信号的数据提供给跟踪数据收集单元。 提供了一种方法和计算机程序产品。
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18.发明申请METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR SAMPLING COMPUTER SYSTEM PERFORMANCE DATA 失效用于采样计算机系统性能数据的方法，系统和计算机程序产品公开(公告)号：US20090210752A1
公开(公告)日：2009-08-20
申请号：US12031727
申请日：2008-02-15
申请人： Jane H. Bartik , Martin Recktenwald , Chung-Lung Kevin Shum , Scott B. Swaney , Patrick M. West, JR.
发明人： Jane H. Bartik , Martin Recktenwald , Chung-Lung Kevin Shum , Scott B. Swaney , Patrick M. West, JR.
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/3466 , G06F11/3476
摘要： A system, method and computer program product for sampling computer system performance data are provided. The system includes a sample buffer to store instrumentation data while capturing trace data in a trace array, where the instrumentation data enables measurement of computer system performance. The system further includes a sample interrupt generator to assert a sample interrupt indicating that the instrumentation data is available to read. The sample interrupt is asserted in response to storing the instrumentation data in the sample buffer.
摘要翻译： 提供了一种用于采样计算机系统性能数据的系统，方法和计算机程序产品。 该系统包括一个样本缓冲区，用于存储仪器数据，同时捕获跟踪阵列中的跟踪数据，其中仪器数据可以测量计算机系统性能。 该系统还包括一个样本中断发生器，用于断言一个样本中断，指示仪器数据可用于读取。 响应于将仪器数据存储在采样缓冲器中，取样中断被置位。
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19.发明申请System, apparatus and method of providing accurate time-based counters for scaling operating frequencies of microprocessors 失效提供精确的基于时间的计数器的系统，装置和方法，用于缩放微处理器的工作频率公开(公告)号：US20070172010A1
公开(公告)日：2007-07-26
申请号：US11340449
申请日：2006-01-26
申请人： Rolf Hilgendorf , Jens Kuenzer , Cedric Lichtenau , Thomas Pflueger , Martin Recktenwald , Andreas Schmid
发明人： Rolf Hilgendorf , Jens Kuenzer , Cedric Lichtenau , Thomas Pflueger , Martin Recktenwald , Andreas Schmid
IPC分类号： H04L7/00
摘要： The illustrative embodiments provide a system, apparatus and method for providing accurate time-based counters for scaling operating frequencies of microprocessors. The system, apparatus and method make use of a time-based counter circuit configuration in which a fixed frequency clock is derived from a PLL of the clock generation circuit of the microprocessor and is used to feed the external and internal timebase logic as well as a timebase accumulator counter. The timebase accumulator counter accumulates the tick events from the timebase logic between two core clocks. The accumulated value is transferred to the core clock domain on every clock edge of a scalable clock and the accumulator is then reset. Because the accumulated ticks are transferred to the core clock domain before the accumulator is reset, no ticks are ever lost using the circuitry of the illustrative embodiment.
摘要翻译： 说明性实施例提供了一种用于提供用于缩放微处理器的操作频率的精确的基于时间的计数器的系统，装置和方法。 系统，装置和方法利用基于时间的计数器电路配置，其中固定频率时钟源自微处理器的时钟产生电路的PLL，并用于馈送外部和内部时基逻辑以及 时基累加器计数器。 时基累加器计数器从两个核心时钟之间的时基逻辑累加tick事件。 累加值在可伸缩时钟的每个时钟沿传输到核心时钟域，然后累加器复位。 因为在累加器复位之前累积的刻度被传送到核心时钟域，所以使用说明性实施例的电路不会丢失任何刻度。
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20.发明授权Microarchitecture, method and computer program product for efficient data gathering from a set of trace arrays 失效微结构，方法和计算机程序产品，用于从一组跟踪数组收集高效数据公开(公告)号：US08127118B2
公开(公告)日：2012-02-28
申请号：US12036540
申请日：2008-02-25
申请人： Patrick M. West, Jr. , Jane H. Bartik , Martin Recktenwald , Chung-Lung K. Shum , Scott B. Swaney
发明人： Patrick M. West, Jr. , Jane H. Bartik , Martin Recktenwald , Chung-Lung K. Shum , Scott B. Swaney
CPC分类号： G06F11/3466
摘要： An architecture for collecting performance data in a processor, that includes: a trace read control unit and a trace data collect unit, each unit coupled to a plurality of trace array and multiplex units for providing performance data, the coupling accomplished by a trace read control bus, a data select bus, a trace row address bus and a data return bus; wherein each of the trace array and multiplex units receives a trace read signal and provides data including trace data and the trace read signal to the trace data collect unit. A method and a computer program product are provided.
摘要翻译： 一种用于在处理器中收集性能数据的架构，其包括：跟踪读取控制单元和跟踪数据收集单元，每个单元耦合到多个跟踪阵列和用于提供性能数据的多路复用单元，所述耦合由跟踪读取控制 总线，数据选择总线，跟踪行地址总线和数据返回总线; 其中每个跟踪阵列和多路复用单元接收跟踪读取信号，并将跟踪数据和跟踪读取信号的数据提供给跟踪数据收集单元。 提供了一种方法和计算机程序产品。
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