System for protection against electrostatic discharges in an electrical circuit
    12.
    发明授权
    System for protection against electrostatic discharges in an electrical circuit 有权
    用于防止电路中的静电放电的系统

    公开(公告)号:US08476711B2

    公开(公告)日:2013-07-02

    申请号:US12176659

    申请日:2008-07-21

    IPC分类号: H01L27/06

    摘要: A gate controlled fin resistance element for use as an electrostatic discharge (ESD) protection element in an electrical circuit has a fin structure having a first connection region, a second connection region and a channel region formed between the first and second connection regions. Furthermore, the fin resistance element has a gate region formed at least over a part of the surface of the channel region. The gate region is electrically coupled to a gate control device, which gate control device controls an electrical potential applied to the gate region in such a way that the gate controlled fin resistance element has a high electrical resistance during a first operating state of the electrical circuit and a lower electrical resistance during a second operating state, which is characterized by the occurrence of an ESD event.

    摘要翻译: 在电路中用作静电放电(ESD)保护元件的栅极控制鳍电阻元件具有鳍状结构,其具有形成在第一和第二连接区域之间的第一连接区域,第二连接区域和沟道区域。 此外,散热片电阻元件具有形成在通道区域的表面的至少一部分上的栅极区域。 栅极区域电耦合到栅极控制装置,栅极控制装置控制施加到栅极区域的电位,使得栅极控制的鳍状电阻元件在电路的第一操作状态期间具有高电阻 并且在第二操作状态期间具有较低的电阻,其特征在于发生ESD事件。

    ESD Clamp Adjustment
    15.
    发明申请
    ESD Clamp Adjustment 有权
    ESD钳位调整

    公开(公告)号:US20120002333A1

    公开(公告)日:2012-01-05

    申请号:US12826983

    申请日:2010-06-30

    IPC分类号: H02H9/04

    摘要: Embodiments of this disclosure relate to electrostatic discharge (ESD) protection techniques. For example, some embodiments include a variable resistor that selectively shunts power of an incoming ESD pulse from a first circuit node to a second circuit node and away from a semiconductor device. A control voltage provided to the variable resistor causes the transistor to change between a fully-off mode where only sub-threshold current, if any, flows; a fully-on mode wherein a maximum amount of current flows; and an analog mode wherein an intermediate and time-varying amount of current flows. In particular, the analog mode allows the ESD protection device to shunt power more precisely than previously achievable, such that the ESD protection device can protect semiconductor devices from ESD pulses.

    摘要翻译: 本公开的实施例涉及静电放电(ESD)保护技术。 例如,一些实施例包括可变电阻器,其选择性地将来自第一电路节点的输入ESD脉冲的功率分流到第二电路节点并远离半导体器件。 提供给可变电阻器的控制电压使得晶体管在只有亚阈值电流(如果有的话)流动的完全关闭模式之间改变; 其中最大量的电流流动的完全启动模式; 以及其中中间和时变量的电流流动的模拟模式。 特别地,模拟模式允许ESD保护装置比先前可实现的更精确地分流功率,使得ESD保护装置可以保护半导体器件免受ESD脉冲。

    Electronic circuit, electronic circuit arrangement and method for producing an electronic circuit
    16.
    发明授权
    Electronic circuit, electronic circuit arrangement and method for producing an electronic circuit 有权
    电子电路,电子电路装置及电子电路的制造方法

    公开(公告)号:US08085518B2

    公开(公告)日:2011-12-27

    申请号:US11436235

    申请日:2006-05-18

    IPC分类号: H02H9/00

    摘要: An electronic circuit and method for producing the electronic circuit, where the electronic circuit includes a functional circuit including at least one multigate functional field effect transistor and an ESD protection circuit including at least one multigate ESD protection field effect transistor. The multigate protection field effect transistor is a transistor that is partially depleted of electrical charge carriers, and the trigger voltage of the multigate protection field effect transistor is less than the trigger voltage of the multigate functional field effect transistor.

    摘要翻译: 一种用于制造电子电路的电子电路和方法,其中电子电路包括包括至少一个多功能场效应晶体管的功能电路和包括至少一个多重ESD保护场效应晶体管的ESD保护电路。 多栅极保护场效应晶体管是部分耗尽电荷载流子的晶体管,并且多栅极保护场效应晶体管的触发电压小于多功能场效应晶体管的触发电压。

    MUGFET WITH INCREASED THERMAL MASS
    20.
    发明申请
    MUGFET WITH INCREASED THERMAL MASS 有权
    MUGFET具有增加的热质量

    公开(公告)号:US20080116515A1

    公开(公告)日:2008-05-22

    申请号:US11561170

    申请日:2006-11-17

    IPC分类号: H01L29/786 H01L21/336

    摘要: Some embodiments discussed herein include a semiconductor having a source region, a drain region and an array of fins operatively coupled to a gate region controlling current flow through the fins between the source region and the drain region. The semiconductor also has at least one cooling element formed at least in part of a material having a heat capacity equal to or larger than the heat capacity of the material of the source region, drain region and array of fins, the cooling elements being in close vicinity to fins of the array of fins electrically isolated from the fins of the array, the source region and the drain region. Other embodiments are also disclosed

    摘要翻译: 本文讨论的一些实施例包括具有源极区域,漏极区域和翅片阵列的半导体,其可操作地耦合到栅极区域,以控制流过源极区域和漏极区域之间的鳍片的电流。 所述半导体还具有至少一部分形成有至少部分热容量等于或大于所述源极区域,漏极区域和散热片阵列的热容量的冷却元件的冷却元件,所述冷却元件处于闭合状态 靠近与阵列的鳍片,源极区域和漏极区域电隔离的翅片阵列的翅片。 还公开了其他实施例