公开(公告)号：US20120273847A1

公开(公告)日：2012-11-01

申请号：US13543943

申请日：2012-07-09

申请人： Ming-Huan Tsai ,  Hui Ouyang ,  Chun-Fai Cheng ,  Wei-Han Fan

发明人： Ming-Huan Tsai ,  Hui Ouyang ,  Chun-Fai Cheng ,  Wei-Han Fan

IPC分类号： H01L27/085

CPC分类号： H01L21/823807 ,  H01L21/02433 ,  H01L21/02639 ,  H01L21/823814 ,  H01L29/7848

摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit devices. An exemplary integrated circuit device achieved by the method has a surface proximity of about 1 nm to about 3 nm and a tip depth of about 5 nm to about 10 nm. The integrated circuit device having such surface proximity and tip depth includes an epi source feature and an epi drain feature defined by a first facet and a second facet of a substrate in a first direction, such as a {111} crystallographic plane of the substrate, and a third facet of the substrate in a second direction, such as a { 100} crystallographic plane of the substrate.

摘要翻译： 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。 通过该方法实现的示例性集成电路器件具有约1nm至约3nm的表面接近度和约5nm至约10nm的尖端深度。 具有这种表面接近度和尖端深度的集成电路器件包括由第一方向（例如衬底的{111}晶体平面）的第一方向上的第一面和第二小面限定的外延源特征和外延漏极特征， 以及在第二方向上的衬底的第三面，例如衬底的{100}晶面。

公开(公告)号：US20110312145A1

公开(公告)日：2011-12-22

申请号：US12816519

申请日：2010-06-16

申请人： Ming-Huan Tsai ,  Chun-Fai Cheng ,  Hui Ouyang ,  Yuan-Hung Chiu ,  Yen-Ming Chen

发明人： Ming-Huan Tsai ,  Chun-Fai Cheng ,  Hui Ouyang ,  Yuan-Hung Chiu ,  Yen-Ming Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/66515 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.

摘要翻译： 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。 在一个实施例中，该方法通过在器件的源极和漏极区域中形成掺杂区域和轻掺杂源极和漏极（LDD）区域来实现改进的控制。 掺杂区域注入与LDD区域相反的掺杂剂类型。

公开(公告)号：US08614132B2

公开(公告)日：2013-12-24

申请号：US13240025

申请日：2011-09-22

申请人： Ming-Huan Tsai ,  Chun-Fai Cheng ,  Hui Ouyang ,  Yuan-Hung Chiu ,  Yen-Ming Chen

发明人： Ming-Huan Tsai ,  Chun-Fai Cheng ,  Hui Ouyang ,  Yuan-Hung Chiu ,  Yen-Ming Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/66515 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.

摘要翻译： 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。 在一个实施例中，该方法通过在器件的源极和漏极区域中形成掺杂区域和轻掺杂源极和漏极（LDD）区域来实现改进的控制。 掺杂区域注入与LDD区域相反的掺杂剂类型。

公开(公告)号：US20120132957A1

公开(公告)日：2012-05-31

申请号：US12956090

申请日：2010-11-30

申请人： Hsueh-Chang Sung ,  Ming-Huan Tsai ,  Hsien-Hsin Lin ,  Chun-Fai Cheng ,  Wei-Han Fan

发明人： Hsueh-Chang Sung ,  Ming-Huan Tsai ,  Hsien-Hsin Lin ,  Chun-Fai Cheng ,  Wei-Han Fan

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/165 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A method for forming a high performance strained source-drain structure includes forming a gate structure on a substrate and forming a pocket implant region proximate to the gate structure. Spacers are formed adjacent to the gate structure. A dry etch forms a recess with a first contour; a wet etch enlarge the recess to a second contour; and a thermal etch enlarges the recess to a third contour. The source-drain structure is then formed in the recess having the third contour.

摘要翻译： 用于形成高性能应变源极 - 漏极结构的方法包括在衬底上形成栅极结构并且形成靠近栅极结构的凹穴注入区域。 隔板与门结构相邻形成。 干蚀刻形成具有第一轮廓的凹部; 湿蚀刻将凹槽放大到第二轮廓; 并且热蚀刻将凹槽放大到第三轮廓。 然后在具有第三轮廓的凹槽中形成源极 - 漏极结构。

公开(公告)号：US08445940B2

公开(公告)日：2013-05-21

申请号：US13543943

申请日：2012-07-09

申请人： Ming-Huan Tsai ,  Hui Ouyang ,  Chun-Fai Cheng ,  Wei-Han Fan

发明人： Ming-Huan Tsai ,  Hui Ouyang ,  Chun-Fai Cheng ,  Wei-Han Fan

IPC分类号： H01L31/072

CPC分类号： H01L21/823807 ,  H01L21/02433 ,  H01L21/02639 ,  H01L21/823814 ,  H01L29/7848

摘要： An integrated circuit device is disclosed. The disclosed device provides improved control over a surface proximity and tip depth of integrated circuit devices. An exemplary integrated circuit device disclosed herein has a surface proximity of about 1 nm to about 3 nm and a tip depth of about 5 nm to about 10 nm. The integrated circuit device having such surface proximity and tip depth includes an epi source feature and an epi drain feature defined by a first facet and a second facet of a substrate in a first direction, such as a {111} crystallographic plane of the substrate, and a third facet of the substrate in a second direction, such as a {100} crystallographic plane of the substrate.

摘要翻译： 公开了一种集成电路器件。 所公开的装置提供对集成电路装置的表面接近度和尖端深度的改进的控制。 本文公开的示例性集成电路器件具有约1nm至约3nm的表面接近度和约5nm至约10nm的尖端深度。 具有这种表面接近度和尖端深度的集成电路器件包括由第一方向（例如衬底的{111}晶体平面）的第一方向上的第一面和第二小面限定的外延源特征和外延漏极特征， 以及在第二方向上的衬底的第三面，例如衬底的{100}晶面。

公开(公告)号：US20120001238A1

公开(公告)日：2012-01-05

申请号：US12827344

申请日：2010-06-30

申请人： Ming-Huan Tsai ,  Hui Ouyang ,  Chun-Fai Cheng ,  Wei-Han Fan

发明人： Ming-Huan Tsai ,  Hui Ouyang ,  Chun-Fai Cheng ,  Wei-Han Fan

IPC分类号： H01L29/78 ,  H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/02433 ,  H01L21/02639 ,  H01L21/823814 ,  H01L29/7848

摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a lightly doped source and drain (LDD) region that acts as an etch stop. The LDD region may act as an etch stop during an etching process implemented to form a recess in the substrate that defines a source and drain region of the device.

摘要翻译： 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。 在一个实施例中，该方法通过形成用作蚀刻停止的轻掺杂源极和漏极（LDD）区域来实现改进的控制。 LDD区域可以在蚀刻工艺期间用作蚀刻停止层，以在衬底中形成限定器件的源极和漏极区域的凹陷。

公开(公告)号：US08455859B2

公开(公告)日：2013-06-04

申请号：US12571604

申请日：2009-10-01

申请人： Ming-Huan Tsai ,  Han-Ting Tsai

发明人： Ming-Huan Tsai ,  Han-Ting Tsai

IPC分类号： H01L29/06 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L21/823418 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7833 ,  H01L29/7848

摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate, a gate structure disposed on a surface of the substrate, and strained structures disposed in the substrate at either side of the gate structure and formed of a semiconductor material different from the semiconductor substrate. Each strained structure has a cross-sectional profile that includes a first portion that extends from the surface of substrate and a second portion that tapers from the first portion at an angle ranging from about 50° to about 70°. The angle is measured with respect to an axis parallel to the surface of the substrate.

摘要翻译： 本公开提供一种半导体器件，其包括半导体衬底，设置在衬底的表面上的栅极结构以及设置在栅极结构的任一侧的衬底中的应变结构，并且由与半导体衬底不同的半导体材料形成。 每个应变结构具有横截面轮廓，该截面轮廓包括从基底表面延伸的第一部分和从第一部分以约50°至约70°的角度逐渐变细的第二部分。 角度相对于平行于基板表面的轴线被测量。

公开(公告)号：US20110079856A1

公开(公告)日：2011-04-07

申请号：US12571604

申请日：2009-10-01

申请人： Ming-Huan Tsai ,  Han-Ting Tsai

发明人： Ming-Huan Tsai ,  Han-Ting Tsai

IPC分类号： H01L27/092 ,  H01L29/78

CPC分类号： H01L21/823418 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7833 ,  H01L29/7848

摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate, a gate structure disposed on a surface of the substrate, and strained structures disposed in the substrate at either side of the gate structure and formed of a semiconductor material different from the semiconductor substrate. Each strained structure has a cross-sectional profile that includes a first portion that extends from the surface of substrate and a second portion that tapers from the first portion at an angle ranging from about 50° to about 70°. The angle is measured with respect to an axis parallel to the surface of the substrate.

摘要翻译： 本公开提供一种半导体器件，其包括半导体衬底，设置在衬底的表面上的栅极结构以及设置在栅极结构的任一侧的衬底中的应变结构，并且由与半导体衬底不同的半导体材料形成。 每个应变结构具有横截面轮廓，该截面轮廓包括从基底表面延伸的第一部分和从第一部分以约50°至约70°的角度逐渐变细的第二部分。 角度相对于平行于基板表面的轴线被测量。

公开(公告)号：US07256137B2

公开(公告)日：2007-08-14

申请号：US11052938

申请日：2005-02-07

申请人： Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue ,  Ju-Wang Hsu ,  Ming-Huan Tsai

发明人： Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue ,  Ju-Wang Hsu ,  Ming-Huan Tsai

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76829 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76832

摘要： A method of manufacturing a semiconductor device is provided comprising the steps of: (a) forming a semiconductor element on a substrate, the semiconductor element having at least one nickel silicide contact region, a first etch stop layer formed over the element and an insulating layer formed over the first etch stop layer; (b) forming an opening through the insulating layer over the contact region at least to the first etch stop layer; (c) removing a portion of the first etch stop layer contacting a selected contact region using a process that does not substantially oxidize with the contact region, to form a contact opening to the contact region; and (d) filling the contact opening with conductive material to form a contact.

摘要翻译： 提供一种制造半导体器件的方法，包括以下步骤：（a）在衬底上形成半导体元件，所述半导体元件具有至少一个硅化镍接触区域，形成在元件上的第一蚀刻停止层和绝缘层 形成在第一蚀刻停止层上; （b）至少在所述第一蚀刻停止层上在所述接触区域上形成穿过所述绝缘层的开口; （c）使用不与接触区域基本上氧化的工艺去除与所选择的接触区域接触的第一蚀刻停止层的一部分，以形成到接触区域的接触开口; 和（d）用导电材料填充接触开口以形成接触。

公开(公告)号：US07223647B2

公开(公告)日：2007-05-29

申请号：US10981925

申请日：2004-11-05

申请人： Ju-Wang Hsu ,  Ming-Huan Tsai ,  Chien-Hao Chen ,  Yi-Chun Huang

发明人： Ju-Wang Hsu ,  Ming-Huan Tsai ,  Chien-Hao Chen ,  Yi-Chun Huang

IPC分类号： H01L21/8238

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/7843 ,  Y10S438/938

摘要： An integrated advanced method for forming a semiconductor device utilizes a sacrificial stress layer as part of a film stack that enables spatially selective silicide formation in the device. The low-resistance portion of the device to be silicided includes NMOS transistors and PMOS transistors. The stressed film may be a tensile or compressive nitride film. An annealing process is carried out prior to the silicide formation process. During the annealing process, the stressed nitride film preferentially remains over either the NMOS transistors or PMOS transistors, but not both, to optimize device performance. A tensile nitride film remains over the NMOS transistors but not the PMOS transistors while a compressive nitride film remains over the PMOS transistors but not the NMOS transistors, during anneal.

摘要翻译： 用于形成半导体器件的集成先进方法利用牺牲应力层作为薄膜堆叠的一部分，其能够在器件中形成空间选择性硅化物。 要被硅化的器件的低电阻部分包括NMOS晶体管和PMOS晶体管。 应力膜可以是拉伸或压缩氮化物膜。 在硅化物形成工艺之前进行退火处理。 在退火过程中，应力氮化物膜优先保留在NMOS晶体管或PMOS晶体管之上，但不能同时保持在两者上，以优化器件性能。 在退火期间，拉伸氮化物膜保留在NMOS晶体管上，而不是PMOS晶体管，而压电氮化物膜保留在PMOS晶体管上，而不保留在NMOS晶体管上。