公开(公告)号：US06884736B2

公开(公告)日：2005-04-26

申请号：US10265937

申请日：2002-10-07

申请人： Chii-Ming Wu ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Chin-Hwa Hsieh ,  Shau-Lin Shue ,  Chu-Yun Fu ,  Ju-Wang Hsu ,  Ming-Huan Tsai ,  Yuan-Hung Chiu

发明人： Chii-Ming Wu ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Chin-Hwa Hsieh ,  Shau-Lin Shue ,  Chu-Yun Fu ,  Ju-Wang Hsu ,  Ming-Huan Tsai ,  Yuan-Hung Chiu

IPC分类号： H01L21/311 ,  H01L21/60 ,  H01L21/768 ,  H01L21/302

CPC分类号： H01L21/76829 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76832

摘要： A method of manufacturing a semiconductor device is provided. A semiconductor element is formed on a substrate. The semiconductor element has at least one nickel silicide contact region, an etch stop layer formed over said element, and an insulating layer formed over said etch stop layer. A portion of the etch stop layer immediately over a selected contact region is removed using a process that does not substantially react with the contact region, to form a contact opening. The contact opening is then filled with a conductive material to form a contact.

摘要翻译： 提供一种制造半导体器件的方法。 半导体元件形成在基板上。 半导体元件具有至少一个硅化镍接触区，在所述元件上形成的蚀刻停止层，以及形成在所述蚀刻停止层上的绝缘层。 使用基本上不与接触区域反应的方法去除在所选择的接触区域上方的蚀刻停止层的一部分，以形成接触开口。 然后用导电材料填充接触开口以形成接触。

公开(公告)号：US07256137B2

公开(公告)日：2007-08-14

申请号：US11052938

申请日：2005-02-07

申请人： Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue ,  Ju-Wang Hsu ,  Ming-Huan Tsai

发明人： Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue ,  Ju-Wang Hsu ,  Ming-Huan Tsai

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76829 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76832

摘要： A method of manufacturing a semiconductor device is provided comprising the steps of: (a) forming a semiconductor element on a substrate, the semiconductor element having at least one nickel silicide contact region, a first etch stop layer formed over the element and an insulating layer formed over the first etch stop layer; (b) forming an opening through the insulating layer over the contact region at least to the first etch stop layer; (c) removing a portion of the first etch stop layer contacting a selected contact region using a process that does not substantially oxidize with the contact region, to form a contact opening to the contact region; and (d) filling the contact opening with conductive material to form a contact.

摘要翻译： 提供一种制造半导体器件的方法，包括以下步骤：（a）在衬底上形成半导体元件，所述半导体元件具有至少一个硅化镍接触区域，形成在元件上的第一蚀刻停止层和绝缘层 形成在第一蚀刻停止层上; （b）至少在所述第一蚀刻停止层上在所述接触区域上形成穿过所述绝缘层的开口; （c）使用不与接触区域基本上氧化的工艺去除与所选择的接触区域接触的第一蚀刻停止层的一部分，以形成到接触区域的接触开口; 和（d）用导电材料填充接触开口以形成接触。

公开(公告)号：US20050158986A1

公开(公告)日：2005-07-21

申请号：US11052938

申请日：2005-02-07

申请人： Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue ,  Ju-Wang Hsu ,  Ming-Huan Tsai

发明人： Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue ,  Ju-Wang Hsu ,  Ming-Huan Tsai

IPC分类号： H01L21/311 ,  H01L21/60 ,  H01L21/768 ,  H01L21/20 ,  H01L21/4763

CPC分类号： H01L21/76829 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76832

摘要： A method of manufacturing a semiconductor device is provided comprising the steps of: (a) forming a semiconductor element on a substrate, the semiconductor element having at least one nickel silicide contact region, a first etch stop layer formed over the element and an insulating layer formed over the first etch stop layer; (b) forming an opening through the insulating layer over the contact region at least to the first etch stop layer; (c) removing a portion of the first etch stop layer contacting a selected contact region using a process that does not substantially oxidize with the contact region, to form a contact opening to the contact region; and (d) filling the contact opening with conductive material to form a contact.

摘要翻译： 提供一种制造半导体器件的方法，包括以下步骤：（a）在衬底上形成半导体元件，所述半导体元件具有至少一个硅化镍接触区域，形成在元件上的第一蚀刻停止层和绝缘层 形成在第一蚀刻停止层上; （b）至少在所述第一蚀刻停止层上在所述接触区域上形成穿过所述绝缘层的开口; （c）使用不与接触区域基本上氧化的工艺去除与所选择的接触区域接触的第一蚀刻停止层的一部分，以形成到接触区域的接触开口; 和（d）用导电材料填充接触开口以形成接触。

公开(公告)号：US06706640B1

公开(公告)日：2004-03-16

申请号：US10292355

申请日：2002-11-12

申请人： Ming-Huan Tsai ,  Ju-Wang Hsu ,  Peng-Fu Hsu ,  Hun-Jan Tao

发明人： Ming-Huan Tsai ,  Ju-Wang Hsu ,  Peng-Fu Hsu ,  Hun-Jan Tao

IPC分类号： H01L21302

CPC分类号： H01L21/28518 ,  H01L21/31116 ,  H01L21/76802

摘要： A plasma etch method for etching a dielectric layer and an etch stop layer to reach a metal silicide layer formed thereunder employs for etching the etch stop layer an etchant gas composition comprising a fluorine containing gas and a nitrogen containing gas, preferably with a carrier gas such as argon or helium, but without an oxygen containing gas or a carbon and oxygen containing gas. The plasma etch method is selective for the etch stop layer with respect to the metal silicide layer, thus maintaining the physical and electrical integrity of the metal silicide layer.

摘要翻译： 用于蚀刻介电层和蚀刻停止层以达到其下形成的金属硅化物层的等离子体蚀刻方法用于蚀刻蚀刻停止层包括含氟气体和含氮气体的蚀刻剂气体组合物，优选地使用载气如 作为氩或氦，但不含含氧气体或含碳和氧的气体。 等离子体蚀刻方法对于蚀刻停止层相对于金属硅化物层是选择性的，从而保持金属硅化物层的物理和电气完整性。

公开(公告)号：US06787455B2

公开(公告)日：2004-09-07

申请号：US10032353

申请日：2001-12-21

申请人： Ming-Huan Tsai ,  Hun-Jan Tao ,  Ju-Wang Hsu ,  Cheng-Ku Chen

发明人： Ming-Huan Tsai ,  Hun-Jan Tao ,  Ju-Wang Hsu ,  Cheng-Ku Chen

IPC分类号： H01L214763

CPC分类号： G03F7/094 ,  H01L21/0274 ,  H01L21/76802

摘要： A method for semiconductor device feature development using a bi-layer photoresist including providing a non-silicon containing photoresist layer over a substrate; providing a silicon containing photoresist over the non-silicon containing photoresist layer; exposing said silicon containing photoresist layer to an activating light source an exposure surface defined by an overlying pattern according to a photolithographic process; developing said silicon containing photoresist layer according to a photolithographic process to reveal a portion the non-silicon containing photoresist layer; and, dry developing said non-silicon containing photoresist layer in a plasma reactor by igniting a plasma from an ambient mixture including at least oxygen, carbon monoxide, and argon.

摘要翻译： 一种使用双层光致抗蚀剂的半导体器件特征显影的方法，包括在衬底上提供不含硅的光致抗蚀剂层; 在含硅光致抗蚀剂层上提供含硅光致抗蚀剂; 将所述含硅光致抗蚀剂层暴露于激活光源，根据光刻工艺由覆盖图案限定的曝光表面; 根据光刻工艺显影所述含硅光致抗蚀剂层以露出含有非硅的光致抗蚀剂层的一部分; 以及通过从包括至少氧，一氧化碳和氩的环境混合物点燃等离子体，在等离子体反应器中干燥显影所述不含硅的光致抗蚀剂层。

公开(公告)号：US20060099745A1

公开(公告)日：2006-05-11

申请号：US10981925

申请日：2004-11-05

申请人： Ju-Wang Hsu ,  Ming-Huan Tsai ,  Chien-Hao Chen ,  Yi-Chun Huang

发明人： Ju-Wang Hsu ,  Ming-Huan Tsai ,  Chien-Hao Chen ,  Yi-Chun Huang

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/7843 ,  Y10S438/938

摘要： An integrated advanced method for forming a semiconductor device utilizes a sacrificial stress layer as part of a film stack that enables spatially selective silicide formation in the device. The low-resistance portion of the device to be silicided includes NMOS transistors and PMOS transistors. The stressed film may be a tensile or compressive nitride film. An annealing process is carried out prior to the silicide formation process. During the annealing process, the stressed nitride film preferentially remains over either the NMOS transistors or PMOS transistors, but not both, to optimize device performance. A tensile nitride film remains over the NMOS transistors but not the PMOS transistors while a compressive nitride film remains over the PMOS transistors but not the NMOS transistors, during anneal.

摘要翻译： 用于形成半导体器件的集成先进方法利用牺牲应力层作为薄膜堆叠的一部分，其能够在器件中形成空间选择性硅化物。 要被硅化的器件的低电阻部分包括NMOS晶体管和PMOS晶体管。 应力膜可以是拉伸或压缩氮化物膜。 在硅化物形成工艺之前进行退火处理。 在退火过程中，应力氮化物膜优先保留在NMOS晶体管或PMOS晶体管之上，但不能同时保持在两者上，以优化器件性能。 在退火期间，拉伸氮化物膜保留在NMOS晶体管上，而不是PMOS晶体管，而压电氮化物膜保留在PMOS晶体管上，而不保留在NMOS晶体管上。

公开(公告)号：US06838381B2

公开(公告)日：2005-01-04

申请号：US10329598

申请日：2002-12-26

申请人： Peng-Fu Hsu ,  Ming-Huan Tsai ,  Baw-Ching Perng ,  Ju-Wang Hsu ,  Yaun-Hung Chiu

发明人： Peng-Fu Hsu ,  Ming-Huan Tsai ,  Baw-Ching Perng ,  Ju-Wang Hsu ,  Yaun-Hung Chiu

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76829

摘要： A method of manufacturing a semiconductor device is provided. A nickel silicide layer (e.g., NiSi) is formed on a substrate. Next, a hydrogen plasma treatment may be performed on the silicide layer, which may induce the formation of metal/silicon hydride bonds in the silicide layer. An etch stop layer is formed over the silicide layer. A dielectric layer is formed over the etch stop layer. An opening is formed in the dielectric layer. A portion of the etch stop layer is etched away at the opening to expose at least a portion of the silicide layer therebeneath. The etch chemistry mixture used during the etching step preferably includes hydrogen gas. The change in sheet resistance for the exposed silicide layer portion at the opening after the etching step, as compared to before the etching step, is preferably not greater than about 0.10 ohms/square.

摘要翻译： 提供一种制造半导体器件的方法。 在衬底上形成硅化镍层（例如NiSi）。 接下来，可以在硅化物层上进行氢等离子体处理，这可能在硅化物层中引起金属/硅氢化物键的形成。 在硅化物层之上形成蚀刻停止层。 在蚀刻停止层上方形成介电层。 在电介质层中形成开口。 蚀刻停止层的一部分在开口处被蚀刻掉以暴露其下面的硅化物层的至少一部分。 在蚀刻步骤期间使用的蚀刻化学混合物优选包括氢气。 与蚀刻步骤之前相比，在蚀刻步骤之后的开口处的暴露的硅化物层部分的薄层电阻的变化优选不大于约0.10欧姆/平方。

公开(公告)号：US07223647B2

公开(公告)日：2007-05-29

申请号：US10981925

申请日：2004-11-05

申请人： Ju-Wang Hsu ,  Ming-Huan Tsai ,  Chien-Hao Chen ,  Yi-Chun Huang

发明人： Ju-Wang Hsu ,  Ming-Huan Tsai ,  Chien-Hao Chen ,  Yi-Chun Huang

IPC分类号： H01L21/8238

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/7843 ,  Y10S438/938

摘要： An integrated advanced method for forming a semiconductor device utilizes a sacrificial stress layer as part of a film stack that enables spatially selective silicide formation in the device. The low-resistance portion of the device to be silicided includes NMOS transistors and PMOS transistors. The stressed film may be a tensile or compressive nitride film. An annealing process is carried out prior to the silicide formation process. During the annealing process, the stressed nitride film preferentially remains over either the NMOS transistors or PMOS transistors, but not both, to optimize device performance. A tensile nitride film remains over the NMOS transistors but not the PMOS transistors while a compressive nitride film remains over the PMOS transistors but not the NMOS transistors, during anneal.

摘要翻译： 用于形成半导体器件的集成先进方法利用牺牲应力层作为薄膜堆叠的一部分，其能够在器件中形成空间选择性硅化物。 要被硅化的器件的低电阻部分包括NMOS晶体管和PMOS晶体管。 应力膜可以是拉伸或压缩氮化物膜。 在硅化物形成工艺之前进行退火处理。 在退火过程中，应力氮化物膜优先保留在NMOS晶体管或PMOS晶体管之上，但不能同时保持在两者上，以优化器件性能。 在退火期间，拉伸氮化物膜保留在NMOS晶体管上，而不是PMOS晶体管，而压电氮化物膜保留在PMOS晶体管上，而不保留在NMOS晶体管上。

公开(公告)号：US20060154478A1

公开(公告)日：2006-07-13

申请号：US11035325

申请日：2005-01-12

申请人： Ju-Wang Hsu ,  Jyu-Horng Shieh ,  Yi-Nien Su ,  Peng-Fu Hsu ,  Hun-Jan Tao

发明人： Ju-Wang Hsu ,  Jyu-Horng Shieh ,  Yi-Nien Su ,  Peng-Fu Hsu ,  Hun-Jan Tao

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  H01L21/76835

摘要： Methods and structures for forming a contact hole structure are disclosed. These methods first form a substantially silicon-free material layer over a substrate. A material layer is formed over the substantially silicon-free material layer. A contact hole is formed within the substantially silicon-free material layer and the material layer without substantially damaging the substrate. In addition, a conductive layer is formed in the contact hole so as to form a contact structure.

摘要翻译： 公开了形成接触孔结构的方法和结构。 这些方法首先在衬底上形成基本上无硅的材料层。 在基本无硅材料层上形成材料层。 在基本无硅的材料层和材料层内形成接触孔，而基本上不损坏衬底。 此外，在接触孔中形成导电层以形成接触结构。

公开(公告)号：US20060063322A1

公开(公告)日：2006-03-23

申请号：US10946494

申请日：2004-09-21

申请人： Ju-Wang Hsu ,  Jyu-Horng Shieh ,  Ju-Chien Chiang

发明人： Ju-Wang Hsu ,  Jyu-Horng Shieh ,  Ju-Chien Chiang

IPC分类号： H01L21/8238 ,  H01L21/302

CPC分类号： H01L29/66553 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/495 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66583

摘要： A semiconductor device provides a gate structure that includes a conductive portion and a high-k dielectric material formed beneath and along sides of the conductive material. An additional gate dielectric material such as a gate oxide may be used in addition to the high-k dielectric material. The method for forming the structure includes forming an opening in an organic material, forming the high-k dielectric material and a conductive material within the opening and over the organic material then using chemical mechanical polishing to remove the high-k dielectric material and conductive material from regions outside the gate region.

摘要翻译： 半导体器件提供了一种栅极结构，其包括在导电材料的下面和沿着导电材料的侧面形成的导电部分和高k电介质材料。 除了高k电介质材料之外，可以使用诸如栅极氧化物的附加栅极介电材料。 形成结构的方法包括在有机材料中形成开口，在开口内和有机材料上形成高k电介质材料和导电材料，然后使用化学机械抛光去除高k电介质材料和导电材料 从门区域外的区域。