公开(公告)号：US20100155929A1

公开(公告)日：2010-06-24

申请号：US12713333

申请日：2010-02-26

Applicant: Chun-Ying Lin ,  Yu-Tang Pan ,  Shih-Wen Chou ,  Geng-Shin Shen

Inventor： Chun-Ying Lin ,  Yu-Tang Pan ,  Shih-Wen Chou ,  Geng-Shin Shen

IPC: H01L25/065 ,  H01L23/52

CPC classification number: H01L25/0657 ,  H01L23/3121 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/04073 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/4824 ,  H01L2224/4918 ,  H01L2224/731 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, a patterned circuit layer and a second chip. The substrate has a first surface and an opposite second surface. The first chip with a first active area and an opposite first rear surface is electrically connected to first surface of substrate by a flip chip bonding process. The patterned circuit layer set on the dielectric layer is electrically connected to the substrate via a bonding wire. The second chip set on the patterned circuit layer has a second active area and a plurality of second pads formed on the second active area, wherein the second bonding pad is electrically connected to the patterned circuit layer.

Abstract translation: 提供了芯片堆叠封装结构和应用，其中芯片堆叠封装结构包括衬底，第一芯片，图案化电路层和第二芯片。 衬底具有第一表面和相对的第二表面。 具有第一有源区和相对的第一后表面的第一芯片通过倒装芯片接合工艺电连接到衬底的第一表面。 设置在电介质层上的图案化电路层通过接合线电连接到基板。 设置在图案化电路层上的第二芯片具有形成在第二有源区上的第二有源区和多个第二焊盘，其中第二焊盘与图案化电路层电连接。

公开(公告)号：US20100120201A1

公开(公告)日：2010-05-13

申请号：US12332362

申请日：2008-12-11

Applicant: Chun-Ying Lin ,  Geng-Shin Shen ,  Po-Kai Hou

Inventor： Chun-Ying Lin ,  Geng-Shin Shen ,  Po-Kai Hou

IPC: H01L21/02

CPC classification number: H01L24/97 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of fabricating a quad flat non-leaded package includes first forming a patterned conductive layer on a sacrificial layer. The patterned conductive layer includes a number of lead sets. A number of chips are attached to the sacrificial layer. Each of the chips is surrounded by one of the lead sets. Each of the chips is electrically connected to one of the lead sets, and a molding compound is formed on the sacrificial layer to cover the patterned conductive layer and the chips. The molding compound and the patterned conductive layer are then cut and singulated, and the sacrificial layer is pre-cut to form a number of recesses on the sacrificial layer. After the molding compound and the patterned conductive layer are cut and singulated and the sacrificial layer is pre-cut, the sacrificial layer is removed.

Abstract translation: 制造四边形扁平非引线封装的方法包括首先在牺牲层上形成图案化的导电层。 图案化导电层包括多个引线组。 许多芯片附着到牺牲层。 每个芯片都被其中一个引线组包围。 每个芯片电连接到一个引线组，并且在牺牲层上形成模制化合物以覆盖图案化的导电层和芯片。 然后将成型化合物和图案化导电层切割并切割，并且牺牲层被预切割以在牺牲层上形成多个凹部。 在模制化合物和图案化的导电层被切割并切割并且牺牲层被预切割之后，去除牺牲层。

公开(公告)号：US20090068797A1

公开(公告)日：2009-03-12

申请号：US12270642

申请日：2008-11-13

Applicant: Geng-Shin Shen ,  Chun-Ying Lin

Inventor： Geng-Shin Shen ,  Chun-Ying Lin

IPC: H01L21/50

CPC classification number: H01L21/4857 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A manufacturing process for a Quad Flat Non-leaded (QFN) chip package structure is provided. First, a conductive layer having a plurality of recesses and a patterned solder resist layer on the conductive layer are provided, wherein the patterned solder resist layer covers the recesses of the conductive layer. A plurality of chips are bonded onto the patterned solder resist layer such that the patterned solder resist layer is between the chips and the conductive layer. The chips are electrically connected to the conductive layer by a plurality of bonding wires. At least one molding compound is formed to encapsulate the conductive layer, the patterned solder resist layer, the chips and the bonding wires. A part of the conductive layer uncovered by the patterned solder resist layer is removed so as to form a patterned conductive layer. Then, the molding compound and the patterned conductive layer are separated.

Abstract translation: 提供了一种用于四边形扁平无铅（QFN）芯片封装结构的制造工艺。 首先，提供在导电层上具有多个凹部的导电层和图案化阻焊层，其中图案化的阻焊层覆盖导电层的凹部。 多个芯片被结合到图案化的阻焊层上，使得图案化的阻焊层位于芯片和导电层之间。 芯片通过多根接合线与导电层电连接。 形成至少一种模塑料以封装导电层，图案化阻焊层，芯片和接合线。 去除由图案化的阻焊层未覆盖的导电层的一部分，以便形成图案化的导电层。 然后，分离模塑料和图案化导电层。

公开(公告)号：US20090068793A1

公开(公告)日：2009-03-12

申请号：US12270627

申请日：2008-11-13

Applicant: Geng-Shin Shen ,  Chun-Ying Lin

Inventor： Geng-Shin Shen ,  Chun-Ying Lin

IPC: H01L21/50

CPC classification number: H01L21/4857 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/4951 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/73215 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A manufacturing process for a chip package structure is provided. First, a patterned conductive layer having a plurality of first openings and a first patterned solder resist layer on the patterned conductive layer are provided. A second patterned solder resist layer is formed on the patterned conductive layer such that the first patterned solder resist layer and the second patterned solder resist layer are disposed at two opposite surfaces of the patterned conductive layer. Chips are bonded onto the first patterned solder resist layer such that the first patterned solder resist layer is between the chips and the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires passing through the first openings. At least one molding compound is formed and the molding compound, the first patterned solder resist layer and the second patterned solder resist layer are separated.

Abstract translation: 提供了一种用于芯片封装结构的制造工艺。 首先，提供在图案化导电层上具有多个第一开口和第一图案化阻焊层的图案化导电层。 在图案化导电层上形成第二图案化阻焊层，使得第一图案化阻焊层和第二图案化阻焊层设置在图案化导电层的两个相对表面处。 芯片被结合到第一图案化阻焊层上，使得第一图案化阻焊层位于芯片和图案化导电层之间。 芯片通过穿过第一开口的多个接合线电连接到图案化的导电层。 形成至少一种模塑料，并且分离模塑料，第一图案化阻焊层和第二图案化阻焊层。

公开(公告)号：US20080157626A1

公开(公告)日：2008-07-03

申请号：US11797243

申请日：2007-05-02

Applicant: Alex Horng ,  I-Yu Huang ,  Yen-Chi Lee ,  Chun-Ying Lin

Inventor： Alex Horng ,  I-Yu Huang ,  Yen-Chi Lee ,  Chun-Ying Lin

IPC: H02N11/00

CPC classification number: H02N1/002

Abstract: To improve the yield, lifetime and driving voltage of the micro scratch drive actuator (SDA), this invention proposes a novel layout design including the etch holes and flange structure designs.Once the etch holes added to the layout of conventional SDA plate, the releasing of structure layer can be accelerated and the accumulated residual charges in the front end of SDA plate is reduced. In this innovative design, a longer lifetime and lower driving voltage of the SDA device can be achieved. On the other hand, adding the flange structure design in the corner of the beam-to-plate conjunction can improve the flexural rigidity of the narrow polysilicon supporting beam which will further enhance the yield of the SDA device and reduce the crack failure under actuating situation.

Abstract translation: 为了提高微刮擦驱动执行器（SDA）的产量，寿命和驱动电压，本发明提出了一种新颖的布局设计，包括蚀刻孔和法兰结构设计。 一旦添加到常规SDA板的布局中的蚀刻孔，可以加速结构层的释放，并减少SDA板的前端中累积的残留电荷。 在这种创新设计中，可以实现SDA器件寿命更长，驱动电压更低。 另一方面，将法兰结构设计添加到梁对板连接的角部可以提高窄多晶硅支撑梁的抗弯刚度，这将进一步提高SDA装置的产量，并减少启动情况下的裂纹破坏 。

公开(公告)号：US20080157625A1

公开(公告)日：2008-07-03

申请号：US11790718

申请日：2007-04-27

Applicant: Alex Horng ,  I-Yu Huang ,  Yen-Chi Lee ,  Chun-Ying Lin

Inventor： Alex Horng ,  I-Yu Huang ,  Yen-Chi Lee ,  Chun-Ying Lin

IPC: H02N11/00 ,  C01B33/02 ,  H01H57/00

CPC classification number: H02N1/002 ,  H02K7/14

Abstract: Based on the voltage-division theory, this invention proposes a new method to decrease the driving voltage of the micro scratch drive actuator (SDA) by using an ultra-low resistivity silicon wafer as substrate. This patent has compared two SDA actuators with the same layout and fabricating processes but under different resistivity of substrate. The SDA fabricated on the ultra-low resistivity silicon wafer has demonstrated a lower driving voltage of only about 4˜12 Vo-p. However, the conventional SDA using normal silicon wafer needs higher driving voltage (30˜75 Vo-p), thus has lower probability for commercial applications. On the other hand, this invention presents a new SDA process to overcome the inherent 2 μm line-width limitation of conventional mask aligner with 4360 Å UV wavelength light source (g-line) and further to reduce the driving voltage of SDA.

Abstract translation: 基于分压理论，本发明提出了一种通过使用超低电阻率硅晶片作为衬底来降低微刮擦驱动致动器（SDA）的驱动电压的新方法。 该专利比较了具有相同布局和制造工艺但在不同电阻率的基板上的两个SDA致动器。 在超低电阻率硅晶片上制造的SDA已经表现出较低的驱动电压仅为约4〜12V o-p 。 然而，使用普通硅晶片的常规SDA需要较高的驱动电压（30〜75V o-p），因此对于商业应用具有较低的概率。 另一方面，本发明提出了一种新的SDA方法，以克服具有4360A紫外线波长光源（g-line）的常规掩模对准器的固有2 mum线宽限制，并进一步降低SDA的驱动电压。

公开(公告)号：US20070088747A1

公开(公告)日：2007-04-19

申请号：US11307796

申请日：2006-02-22

Applicant: Chih-Chuan Cheng ,  Tsai-Chuang Wang ,  Chun-Ying Lin

Inventor： Chih-Chuan Cheng ,  Tsai-Chuang Wang ,  Chun-Ying Lin

IPC: G06F17/00

CPC classification number: G06F16/4387 ,  G06F16/48

Abstract: An automatic multimedia searching method and the multimedia downloading system thereof are provided, which are capable of increasing user's convenience on multimedia searching and downloading events. The method includes the following steps. First, an electronic device which stores a multimedia file and a data source connection are provided. Next, a multimedia file is played. When playing the multimedia file, the electronic device automatically searches the data source for multimedia files having the same content as the content of the information tag in the multimedia file. Finally, the found multimedia files are displayed on the electronic device.

Abstract translation: 提供了一种自动多媒体搜索方法及其多媒体下载系统，其能够增加用户对多媒体搜索和下载事件的便利。 该方法包括以下步骤。 首先，提供存储多媒体文件和数据源连接的电子装置。 接下来，播放多媒体文件。 当播放多媒体文件时，电子设备自动搜索具有与多媒体文件中的信息标签的内容相同内容的多媒体文件的数据源。 最后，找到的多媒体文件显示在电子设备上。

公开(公告)号：US20060110570A1

公开(公告)日：2006-05-25

申请号：US11284478

申请日：2005-11-22

Applicant: Ru-Lin Yeh ,  Chung-Fa Chen ,  Chun-Ying Lin ,  Wei-Hsiang Wang

Inventor： Ru-Lin Yeh ,  Chung-Fa Chen ,  Chun-Ying Lin ,  Wei-Hsiang Wang

IPC: B32B3/02

CPC classification number: G11B7/244 ,  G11B7/24038 ,  G11B7/243 ,  G11B7/2467 ,  G11B7/2472 ,  G11B7/2534 ,  G11B7/258 ,  G11B7/26 ,  G11B2007/2431 ,  G11B2007/24312

Abstract: A dual-layer recordable optical disc includes a first recording layer and a second recording layer disposed on the first recording layer. The first recording layer is made of organic material, and the second recording layer is made of inorganic material. The optical disc may further includes a first substrate, a second substrate and a bonding layer. The first recording layer includes a dye recording layer disposed on the first substrate, and a first reflection layer disposed on the dye recording layer, whereas the second recording layer includes an inorganic recording layer and a second reflection layer disposed on the inorganic recording layer. In addition, the second substrate is disposed on the second reflection layer, and the bonding layer is disposed between the first reflection layer and the inorganic recording layer. A manufacturing process of the optical disc is also provided to increase production yield and lower manufacturing cost.

Abstract translation: 双层可记录光盘包括设置在第一记录层上的第一记录层和第二记录层。 第一记录层由有机材料制成，第二记录层由无机材料制成。 光盘还可以包括第一基板，第二基板和接合层。 第一记录层包括设置在第一基板上的染料记录层和设置在染料记录层上的第一反射层，而第二记录层包括设置在无机记录层上的无机记录层和第二反射层。 此外，第二基板设置在第二反射层上，并且接合层设置在第一反射层和无机记录层之间。 还提供了光盘的制造工艺以提高产量并降低制造成本。

公开(公告)号：US06961302B2

公开(公告)日：2005-11-01

申请号：US10065679

申请日：2002-11-08

Applicant: Shyh-yeu Wang ,  Biing-Hwang Lin ,  Chun-Ying Lin

Inventor： Shyh-yeu Wang ,  Biing-Hwang Lin ,  Chun-Ying Lin

IPC: G11B7/09 ,  G11B7/24 ,  G11B7/246 ,  G11B7/2472 ,  G11B7/257 ,  G11B7/258 ,  G11B7/26

CPC classification number: G11B7/246 ,  G11B7/0938 ,  G11B7/24 ,  G11B7/2472 ,  G11B7/248 ,  G11B7/257 ,  G11B7/258 ,  G11B2007/2571 ,  G11B2007/25711 ,  G11B2007/25713 ,  G11B2007/25715 ,  G11B2007/25716 ,  Y10T428/21

Abstract: A method and structure for intensifying track seeking signals from an optical disk, in particular, a recordable digital versatile disk (DVD-R). With the addition of an optical correction layer between a dye material layer and a reflection layer inside the DVD-R, track-seeking signals of the optical disk are intensified and recording quality of the optical disk is improved. The optical correction layer is a transparent or semi-transparent layer made from inorganic materials. The optical correction layer is formed over the dye material layer in a sputtering process.

Abstract translation: 一种用于从光盘，特别是可记录数字通用盘（DVD-R）增强追踪信号的方法和结构。 通过在DVD-R内部的染料材料层和反射层之间添加光学校正层，光盘的追踪信号被增强，并且提高了光盘的记录质量。 光学校正层是由无机材料制成的透明或半透明层。 在溅射工艺中，在染料材料层上形成光学校正层。

公开(公告)号：US07851896B2

公开(公告)日：2010-12-14

申请号：US12201236

申请日：2008-08-29

Applicant: Geng-Shin Shen ,  Chun-Ying Lin ,  Shih-Wen Chou

Inventor： Geng-Shin Shen ,  Chun-Ying Lin ,  Shih-Wen Chou

IPC: H01L23/495 ,  H01L23/12

CPC classification number: H01L21/6835 ,  H01L21/4832 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49534 ,  H01L23/49558 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A Quad Flat Non-leaded (QFN) chip package including a patterned conductive layer, a first solder resist layer, a chip, a plurality of bonding wires and a molding compound is provided. The patterned conductive layer has a first surface and a second surface opposite to each other. The first solder resist layer is disposed on the first surface, wherein a part of the first surface is exposed by the first solder resist layer. The chip is disposed on the first solder resist layer, wherein the first solder resist layer is between the patterned conductive layer and the chip. The bonding wires are electrically connected to the chip and the patterned conductive layer exposed by the first solder resist layer. The molding compound encapsulates the pattern conductive layer, the first solder resist layer, the chip and the bonding wires.

Abstract translation: 提供了包括图案化导电层，第一阻焊层，芯片，多个接合线和模塑料的四平坦非导体（QFN）芯片封装。 图案化导电层具有彼此相对的第一表面和第二表面。 第一阻焊层设置在第一表面上，其中第一表面的一部分被第一阻焊层暴露。 芯片设置在第一阻焊层上，其中第一阻焊层位于图案化导电层和芯片之间。 接合线与第一阻焊层暴露的芯片和图案化的导电层电连接。 模塑料封装图形导电层，第一阻焊层，芯片和接合线。