公开(公告)号：US20080258233A1

公开(公告)日：2008-10-23

申请号：US11738968

申请日：2007-04-23

Applicant: Ru-Shang Hsiao ,  Min Cao ,  Chung-Te Lin ,  Ta-Ming Kuan ,  Cheng-Tung Hsu

Inventor： Ru-Shang Hsiao ,  Min Cao ,  Chung-Te Lin ,  Ta-Ming Kuan ,  Cheng-Tung Hsu

IPC: H01L29/76

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped drains are formed. Thereafter, new spacers are formed and the stress-inducing layer is recessed. One or more additional implants may be performed to complete source/drain regions. In an embodiment, the PMOS transistor may be formed on the same substrate as one or more NMOS transistors. Dual etch stop layers may also be formed over the PMOS and/or the NMOS transistors.

Abstract translation: 提供具有局部应力源的诸如PMOS晶体管的半导体器件。 凹槽形成在栅电极的相对侧上，使得凹槽通过假间隔件从栅电极偏移。 这些凹部填充有应力诱导层。 去除虚拟凹槽并形成轻掺杂的排水沟。 此后，形成新的间隔物并且应力诱导层凹陷。 可以执行一个或多个附加植入物以完成源极/漏极区域。 在一个实施例中，PMOS晶体管可以形成在与一个或多个NMOS晶体管相同的衬底上。 也可以在PMOS和/或NMOS晶体管上形成双重蚀刻停止层。

公开(公告)号：US07432149B2

公开(公告)日：2008-10-07

申请号：US11290914

申请日：2005-11-30

Applicant: I-Lu Wu ,  Chung-Te Lin ,  Tan-Chen Lee

Inventor： I-Lu Wu ,  Chung-Te Lin ,  Tan-Chen Lee

IPC: H01L21/8238

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/785

Abstract: Methods and structures for CMOS devices with hybrid crystal orientations using double SOI substrates is provided. In accordance with preferred embodiments, a manufacturing sequence includes the steps of forming an SOI silicon epitaxy layer after the step of forming shallow trench isolation regions. The preferred sequence allows hybrid SOI CMOS fabrication without encountering problems caused by forming STI regions after epitaxy. A preferred device includes an NFET on a {100} crystal orientation and a PFET on a {110} crystal orientation. An NMOS channel may be oriented along the direction, which is the direction of maximum electron mobility for a {100} substrate. A PMOS channel may be oriented along the direction, which is the direction where hole mobility is maximum for a {110} substrate.

Abstract translation: 提供了使用双重SOI衬底的具有混合晶体取向的CMOS器件的方法和结构。 根据优选实施例，制造顺序包括在形成浅沟槽隔离区的步骤之后形成SOI硅外延层的步骤。 优选的顺序允许混合SOI CMOS制造，而不会遇到在外延后形成STI区域引起的问题。 优选的器件包括{100}晶体取向的NFET和{110}晶体取向的PFET。 可以沿着<100>方向取向NMOS沟道，这是{100}衬底的最大电子迁移率的方向。 可以沿着<110>方向取向PMOS沟道，这是{110}衬底的空穴迁移率最大的方向。

公开(公告)号：US20080179689A1

公开(公告)日：2008-07-31

申请号：US11669870

申请日：2007-01-31

Applicant: Tan-Chen Lee ,  Chung-Te Lin ,  Kuang-Hsin Chen ,  Chi-Hsi Wu ,  Di-Houng Lee ,  Cheng-Hung Chang

Inventor： Tan-Chen Lee ,  Chung-Te Lin ,  Kuang-Hsin Chen ,  Chi-Hsi Wu ,  Di-Houng Lee ,  Cheng-Hung Chang

IPC: H01L29/78 ,  H01L21/441

CPC classification number: H01L21/28518 ,  H01L21/76829 ,  H01L29/665

Abstract: Disclosed herein are various embodiments of techniques for preventing silicide stringer or encroachment formation during metal salicide formation in semiconductor devices. The disclosed technique involves depositing a protective layer, such as a nitride or other dielectric layer, over areas of the semiconductor device where metal silicide formation is not desired because such formation detrimentally affects device performance. For example, silicon particles that may remain in device features that are formed through silicon oxidation, such as under the gate sidewall spacers and proximate to the perimeter of shallow trench isolation structures, are protected from reacting with metal deposited to form metal silicide in certain areas of the device. As a result, silicide stringers or encroachment in undesired areas is reduced or eliminated by the protective layer.

Abstract translation: 本文公开了用于在半导体器件中的金属自对准硅化物形成期间防止硅化物纵梁或侵入形成的技术的各种实施例。 所公开的技术包括在不需要金属硅化物形成的半导体器件的区域上沉积诸如氮化物或其它电介质层的保护层，因为这种形成不利地影响器件性能。 例如，可以保留在通过硅氧化形成的器件特征中的硅颗粒，例如在栅极侧壁间隔物附近并且靠近浅沟槽隔离结构的周边，防止在某些区域沉积以形成金属硅化物的金属反应 的设备。 结果，通过保护层减少或消除了硅化物桁条或侵入不期望的区域。

公开(公告)号：US06444541B1

公开(公告)日：2002-09-03

申请号：US09638646

申请日：2000-08-14

Applicant: Jun-Yang Lai ,  Jih-Hwa Wang ,  Chou-Jie Tsai ,  Chin-Te Huang ,  Su-Yu Yeh ,  Meng-Shiun Shieh ,  Jang-Cheng Hsieh ,  Chung-Te Lin

Inventor： Jun-Yang Lai ,  Jih-Hwa Wang ,  Chou-Jie Tsai ,  Chin-Te Huang ,  Su-Yu Yeh ,  Meng-Shiun Shieh ,  Jang-Cheng Hsieh ,  Chung-Te Lin

IPC: H01L2176

CPC classification number: H01L21/76232

Abstract: A method for forming lining oxide in an opening for a shallow trench isolation and a method for forming a shallow trench isolation incorporating a lining oxide layer are described. In the method for forming lining oxide, a silicon substrate is first provided, followed by a process of forming a pad oxide layer and a silicon nitride mask sequentially on top of the silicon substrate. A trench opening is then patterned and formed in the silicon substrate for the shallow trench isolation. The silicon substrate is then annealed at a temperature of at least 1,000° C. in a furnace in an environment that contains not more than 10 vol. % oxygen. A lining oxide layer is formed in the same furnace used for annealing the structure of the trench opening in the silicon substrate.

Abstract translation: 描述了在用于浅沟槽隔离的开口中形成衬里氧化物的方法和形成包含衬里氧化物层的浅沟槽隔离的方法。 在形成衬垫氧化物的方法中，首先提供硅衬底，然后依次在硅衬底的顶部上形成衬垫氧化物层和氮化硅掩模的工艺。 然后将沟槽开口图案化并形成在用于浅沟槽隔离的硅衬底中。 然后将硅衬底在至少1000℃的温度下在炉中在包含不超过10体积％的环境中退火。 ％氧气。 在用于退火硅衬底中的沟槽开口的结构的同一炉中形成衬里氧化物层。

公开(公告)号：US07611937B2

公开(公告)日：2009-11-03

申请号：US11281029

申请日：2005-11-17

Applicant: Chung-Te Lin ,  I-Lu Wu ,  Mariam Sadaka

Inventor： Chung-Te Lin ,  I-Lu Wu ,  Mariam Sadaka

IPC: H01L21/336 ,  H01L21/8234

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/78

Abstract: A method of forming a semiconductor structure having a hybrid crystal orientation and forming MOSFETs having improved performance on the semiconductor structure is provided. The method includes providing a substrate comprising a buried oxide (BOX) on a first semiconductor layer, and a second semiconductor layer on the BOX, wherein the first and second semiconductor layers have a first and a second crystal orientation, respectively, and wherein the substrate comprises a first region and a second region. An isolation structure is formed in the second region extending to the first semiconductor layer. A trench is then formed in the isolation structure, exposing the first semiconductor layer. A semiconductor material is epitaxially grown in the trench. The method further includes forming a MOSFET of a first type on the second semiconductor layer and a MOSFET of an opposite type than the first type on the epitaxially grown semiconductor material.

Abstract translation: 提供一种形成具有混合晶体取向的半导体结构并形成在半导体结构上具有改进性能的MOSFET的方法。 该方法包括在第一半导体层上提供包括掩埋氧化物（BOX）的衬底和BOX上的第二半导体层，其中第一和第二半导体层分别具有第一和第二晶体取向，并且其中衬底 包括第一区域和第二区域。 在延伸到第一半导体层的第二区域中形成隔离结构。 然后在隔离结构中形成沟槽，暴露第一半导体层。 半导体材料在沟槽中外延生长。 该方法还包括在外延生长的半导体材料上在第二半导体层上形成第一类型的MOSFET和与第一类型相反的MOSFET。

公开(公告)号：US20060292834A1

公开(公告)日：2006-12-28

申请号：US11281029

申请日：2005-11-17

Applicant: Chung-Te Lin ,  I-Lu Wu ,  Mariam Sadaka

Inventor： Chung-Te Lin ,  I-Lu Wu ,  Mariam Sadaka

IPC: H01L21/20 ,  H01L21/36

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/78

Abstract: A method of forming a semiconductor structure having a hybrid crystal orientation and forming MOSFETs having improved performance on the semiconductor structure is provided. The method includes providing a substrate comprising a buried oxide (BOX) on a first semiconductor layer, and a second semiconductor layer on the BOX, wherein the first and second semiconductor layers have a first and a second crystal orientation, respectively, and wherein the substrate comprises a first region and a second region. An isolation structure is formed in the second region extending to the first semiconductor layer. A trench is then formed in the isolation structure, exposing the first semiconductor layer. A semiconductor material is epitaxially grown in the trench. The method further includes forming a MOSFET of a first type on the second semiconductor layer and a MOSFET of an opposite type than the first type on the epitaxially grown semiconductor material.

公开(公告)号：US06583017B2

公开(公告)日：2003-06-24

申请号：US09927072

申请日：2001-08-10

Applicant: Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So-Wein Kuo

Inventor： Chu-Wei Hu ,  Jiue-Wen Weng ,  Chung-Te Lin ,  So-Wein Kuo

IPC: H01L21336

CPC classification number: H01L29/66492 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/7834

Abstract: A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the S/D regions a gate electrode has been created with elevated S/D regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and disposable spacers. By forming the gate spacers and the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and spacers where the gate poly protrudes above the spacers thus enhancing the formation of silicide.

Abstract translation: 一种用于产生具有升高的源极/漏极区域的自对准沟道植入物的方法。 在硅衬底的顶部形成薄的电介质层，在该电介质上沉积厚层氧化物。 将开口暴露并蚀刻通过氧化物层，通过电介质并进入下面的硅衬底，在衬底中形成浅沟槽。 通过执行通道注入LDD注入，口袋注入，形成栅极间隔物和电极，移除厚层氧化物并形成S / D区域，栅极电极已经产生了升高的S / D区域。 通过形成栅极间隔物，进行沟道注入，形成栅电极，去除厚层氧化物并执行S / D注入，已经产生了具有升高的S / D区域和一次性间隔物的栅电极。 通过形成栅极间隔物和栅电极，去除厚层氧化物并进行S / D注入，已经产生了具有升高的S / D区域和间隔物的栅电极，其中栅极聚合物突出在间隔物上方，从而增强了硅化物的形成 。

公开(公告)号：US6057207A

公开(公告)日：2000-05-02

申请号：US47542

申请日：1998-03-25

Applicant: Chung-Te Lin ,  Chin-Hsiun Ho

Inventor： Chung-Te Lin ,  Chin-Hsiun Ho

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76229 ,  H01L21/76224

Abstract: A method of planarizing a non-conformal oxide layer 40 forming shallow trench isolation between active areas 12 in a substrate. The invention uses a first chemical-mechanical polish (CMP) step to form openings 50 only over wide active areas. An etch is used to remove oxide 40 from only over the wide active areas 12A. A second CMP step is used to planarized the oxide layer 40. The invention begins by forming spaced trenches 30 in said substrate 10 defining active areas 12. A first insulating layer 40 composed of a non-conformal silicon oxide is formed by a HDPCVD process over the substrate and fills the trenches 30. A etch barrier layer 44 is formed over the first insulating layer 40. In a first chemical-mechanical polish (CMP) step, the conformal etch barrier layer 44 over only the wide raised portions 12A is polished to form a self-aligned first openings 50. The chemical-mechanical polishing of the conformal etch barrier layer forms a self-aligned etch mask. The first insulating layer 40 is then etched through at least the first opening 50 to expose a first barrier layer 24 over the wide active areas 12A. In a second CMP step, the etch barrier layer 44 is removed and the first insulating layer 40 is planarized to fill the shallow trenches 30.

Abstract translation: 在衬底中的有源区域12之间形成浅沟槽隔离的非保形氧化物层40的平面化方法。 本发明使用第一化学机械抛光（CMP）步骤仅在宽的有效区域上形成开口50。 使用蚀刻仅从宽的有源区域12A移除氧化物40。 使用第二CMP步骤对氧化物层40进行平坦化。本发明通过在限定有源区域12的所述衬底10中形成间隔开的沟槽30开始。由非保形氧化硅构成的第一绝缘层40通过HDPCVD工艺形成 衬底并填充沟槽30.蚀刻阻挡层44形成在第一绝缘层40的上方。在第一化学机械抛光（CMP）步骤中，只有宽的凸起部分12A上的共形蚀刻阻挡层44被抛光到 形成自对准的第一开口50.保形蚀刻阻挡层的化学机械抛光形成自对准的蚀刻掩模。 然后，通过至少第一开口50蚀刻第一绝缘层40，以在宽的有源区域12A上露出第一阻挡层24。 在第二CMP步骤中，去除蚀刻阻挡层44，并且平坦化第一绝缘层40以填充浅沟槽30。

公开(公告)号：US08546860B2

公开(公告)日：2013-10-01

申请号：US13494769

申请日：2012-06-12

Applicant: Ru-Shang Hsiao ,  Nai-Wen Cheng ,  Chung-Te Lin ,  Chien-Hsien Tseng ,  Shou-Gwo Wuu

Inventor： Ru-Shang Hsiao ,  Nai-Wen Cheng ,  Chung-Te Lin ,  Chien-Hsien Tseng ,  Shou-Gwo Wuu

IPC: H01L31/113 ,  H01L31/173

CPC classification number: H01L27/1463 ,  H01L21/324 ,  H01L21/823878 ,  H01L22/34 ,  H01L27/14689 ,  H01L29/7842

Abstract: This disclosure relates to an active pixel cell including a shallow trench isolation (STI) structure. The active pixel cell further includes a photodiode neighboring the STI structure, where a first stress resulted from substrate processing prior to deposition of a pre-metal dielectric layer increases dark current and white cell counts of a photodiode of the active pixel cell. The active pixel cell further includes a transistor, where the transistor controls the operation of the active pixel cell. The active pixel cell further includes a stress layer over the photodiode, the STI structure, and the transistor, and the stress layer has a second stress that counters the first stress exerted on the substrate, and the second stress reduces the dark current and the white cell counts caused by the first stress.

Abstract translation: 本公开涉及包括浅沟槽隔离（STI）结构的有源像素单元。 有源像素单元还包括与STI结构相邻的光电二极管，其中在沉积预金属介电层之前由衬底处理产生的第一应力增加了有源像素单元的光电二极管的暗电流和白细胞计数。 有源像素单元还包括晶体管，其中晶体管控制有源像素单元的操作。 有源像素单元还包括光电二极管上的应力层，STI结构和晶体管，并且应力层具有对施加在衬底上的第一应力进行反映的第二应力，并且第二应力减小暗电流和白色 细胞计数由第一次压力引起。

公开(公告)号：US20120043618A1

公开(公告)日：2012-02-23

申请号：US13284594

申请日：2011-10-28

Applicant: Lee-Chung Lu ,  Chung-Te Lin ,  Yen-Sen Wang ,  Yao-Jen Chuang ,  Gwan Sin Chang

Inventor： Lee-Chung Lu ,  Chung-Te Lin ,  Yen-Sen Wang ,  Yao-Jen Chuang ,  Gwan Sin Chang

IPC: H01L27/092

CPC classification number: G06F17/5068 ,  G03F1/36

Abstract: Stress engineering for PMOS and NMOS devices is obtained with a compressive stressor layer over the PMOS device, wherein the compressive stressor layer has the shape of a polygon when viewed from a top down perspective, and wherein the polygon includes a recess defined in its periphery. The NMOS device has a tensile stress layer wherein the tensile stressor layer has the shape of a polygon when viewed from the top down perspective, wherein the polygon includes a protrusion in its periphery, the protrusion extending into the recess of the first stressor layer. Thus, stress performance for both devices can be improved without violating design rules.

Abstract translation: 通过PMOS器件上的压应力层获得用于PMOS和NMOS器件的应力工程，其中当从顶部向下观察时，压应力层具有多边形的形状，并且其中多边形包括限定在其周边的凹部。 NMOS器件具有拉伸应力层，其中从顶部向下观察时，拉伸应力层具有多边形的形状，其中多边形包括在其周边的突起，突出部延伸到第一应力层的凹部中。 因此，可以在不违反设计规则的情况下改善两种装置的应力性能。