公开(公告)号：US20050033938A1

公开(公告)日：2005-02-10

申请号：US10940434

申请日：2004-09-14

申请人： Gordon Davis ,  Marco Heddes ,  Ross Leavens ,  Mark Rinaldi

发明人： Gordon Davis ,  Marco Heddes ,  Ross Leavens ,  Mark Rinaldi

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F15/00

CPC分类号： G06F9/3013 ,  G06F9/30087 ,  G06F9/3885

摘要： A network processor utilizes protocol processor units (PPUs) to provide instruction communication for the network. Each PPU includes a core language processor (CLP). Each CLP contains general purpose registers and includes a coprocessor that contains scalar registers and array registers. The CLP controls and instructs a plurality of coprocessors that run in parallel with the CLP. Each coprocessor is a specialized hardware assist engine having direct access to the CLP registers and arrays through two sets of interface signals, a coprocessor execution interface and a coprocessor data interface.

摘要翻译： 网络处理器利用协议处理器单元（PPU）为网络提供指令通信。 每个PPU包括核心语言处理器（CLP）。 每个CLP都包含通用寄存器，包括一个包含标量寄存器和数组寄存器的协处理器。 CLP控制并指示与CLP并行运行的多个协处理器。 每个协处理器是专门的硬件辅助引擎，可以通过两组接口信号，协处理器执行接口和协处理器数据接口直接访问CLP寄存器和阵列。

公开(公告)号：US20050050188A1

公开(公告)日：2005-03-03

申请号：US10654139

申请日：2003-09-03

申请人： Gordon Davis ,  Marco Heddes ,  Dongming Hwang

发明人： Gordon Davis ,  Marco Heddes ,  Dongming Hwang

IPC分类号： G06F15/173 ,  G06F17/30

CPC分类号： G06F17/30955 ,  Y10S707/99933 ,  Y10S707/99942

摘要： A procedure is used to provide data structures that handle large numbers of active data entries and a high rate of additions and deletions of active entries. The procedure utilizes one or more of the following modifications. Timers are removed from individual session table entries and are linked via pointers. Bilateral links are established between the session table and the timer structure. Aging/timer checks are applied to the timer control block (TCB). A chain of TCBs, optionally including an excess of blocks, may be used along with packing of multiple TCBs into a single memory location. This excess of blocks permits a terminated session to continue to occupy a TCB until the timer process progresses to that block location in the chain of blocks.

摘要翻译： 一个过程用于提供处理大量活动数据条目的数据结构以及高活动条目的添加和删除率。 该过程利用以下一个或多个修改。 定时器从单个会话表条目中删除，并通过指针进行链接。 在会话表和定时器结构之间建立双向链路。 老化/定时器检查应用于定时器控制块（TCB）。 可以使用可选地包括多余块的TCB链，以及将多个TCB打包到单个存储器位置中。 这个多余的块允许终止的会话继续占用TCB，直到定时器进程前进到块链中的块位置。

公开(公告)号：US20050022196A1

公开(公告)日：2005-01-27

申请号：US10915983

申请日：2004-08-11

申请人： Gordon Davis ,  Marco Heddes ,  Ross Leavens ,  Fabrice Verplanken

发明人： Gordon Davis ,  Marco Heddes ,  Ross Leavens ,  Fabrice Verplanken

IPC分类号： G06F9/46 ,  G06F9/38 ,  G06F9/48 ,  G06F9/52 ,  G06F15/16

CPC分类号： G06F9/3802 ,  G06F9/3851

摘要： A mechanism controls a multi-thread processor so that when a first thread encounters a latency event for a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back to the original thread. The mechanism grants full control to the alternate execution thread when a latency event for a second predefined time interval is encountered. The first predefined time interval is termed short latency event whereas the second time interval is termed long latency event.

摘要翻译： 机制控制多线程处理器，使得当第一线程遇到第一预定义时间间隔的等待时间事件时，临时控制在第一预定义时间间隔的持续时间内被传送到备用执行线程，然后返回到原始线程。 当遇到第二个预定义时间间隔的延迟事件时，机制将授权对备用执行线程的完全控制。 第一预定时间间隔称为短延迟事件，而第二时间间隔称为长延迟事件。

公开(公告)号：US20060026342A1

公开(公告)日：2006-02-02

申请号：US10899937

申请日：2004-07-27

申请人： Jean Calvignac ,  Chih-Jen Chang ,  Gordon Davis ,  Fabrice Verplanken

发明人： Jean Calvignac ,  Chih-Jen Chang ,  Gordon Davis ,  Fabrice Verplanken

IPC分类号： G06F12/00

CPC分类号： G06F13/1642

摘要： Access arbiters are used to prioritize read and write access requests to individual memory banks in DRAM memory devices, particularly fast cycle DRAMs. This serves to optimize the memory bandwidth available for the read and the write operations by avoiding consecutive accesses to the same memory bank and by minimizing dead cycles. The arbiter first divides DRAM accesses into write accesses and read accesses. The access requests are divided into accesses per memory bank with a threshold limit imposed on the number of accesses to each memory bank. The write receive packets are rotated among the banks based on the write queue status. The status of the write queue for each memory bank may also be used for system flow control. The arbiter also typically includes the ability to determine access windows based on the status of the command queues, and to perform arbitration on each access window.

摘要翻译： 访问仲裁器被用于将对DRAM存储器件，特别是快速循环DRAM中的各个存储体的读取和写入访问请求进行优先级排序。 这用于通过避免对同一存储体的连续访问并且通过最小化死循环来优化用于读取和写入操作的存储器带宽。 仲裁器首先将DRAM访问划分为写访问和读访问。 访问请求被划分为每个存储体的访问，并且对每个存储体的访问次数施加了阈值限制。 基于写入队列状态，写入接收数据包在存储体之间旋转。 每个存储体的写入队列的状态也可以用于系统流控制。 仲裁器还通常包括基于命令队列的状态来确定访问窗口的能力，并且在每个访问窗口上执行仲裁。

公开(公告)号：US20080013541A1

公开(公告)日：2008-01-17

申请号：US11776807

申请日：2007-07-12

申请人： Jean Calvignac ,  Gordon Davis

发明人： Jean Calvignac ,  Gordon Davis

IPC分类号： H04L12/54

CPC分类号： H04L49/602 ,  H04L49/354 ,  H04L49/604 ,  H04L69/22

摘要： A method and structure are disclosed for dispatching appropriate data to a network processing system comprising an improved technique for extracting protocol header fields for use by the network processor. This technique includes basic classification of a packet according to the types of protocol headers present in the packet. Based on the results of the classification, specific parameter fields are extracted from corresponding headers. All such parameter fields from one or more protocol headers in the packet are concatenated into a compressed dispatch message. Multiples of such dispatch messages are bundled into a single composite dispatch message. Thus, selected header fields from N packets are passed to the network processor in a single composite dispatch message, increasing the network processor's packet forwarding capacity by a factor of N. Likewise, multiple enqueue messages are bundled into a single composite enqueue message to direct enqueue and frame alterations to be taken on the bundle of N packets.

摘要翻译： 公开了一种用于将适当数据发送到网络处理系统的方法和结构，所述网络处理系统包括用于提取网络处理器使用的协议头域的改进技术。 该技术包括根据分组中存在的协议报头的类型对分组的基本分类。 根据分类结果，从相应的标题中提取特定参数字段。 来自分组中的一个或多个协议报头的所有这些参数字段被连接成压缩的调度消息。 这种分派消息的倍数被捆绑成单个复合调度消息。 因此，来自N个分组的选择的报头字段以单个复合调度消息传递到网络处理器，从而将网络处理器的分组转发能力提高N倍。同样地，多个入队消息被捆绑到单个复合入口消息中以引导入队 并且对N个分组的束进行帧改变。

公开(公告)号：US20070294471A1

公开(公告)日：2007-12-20

申请号：US11832220

申请日：2007-08-01

申请人： Jean Calvignac ,  Chih-jen Chang ,  Gordon Davis ,  Fabrice Verplanken

发明人： Jean Calvignac ,  Chih-jen Chang ,  Gordon Davis ,  Fabrice Verplanken

IPC分类号： G06F12/00

CPC分类号： G06F13/1642

摘要： Access arbiters are used to prioritize read and write access requests to individual memory banks in DRAM memory devices, particularly fast cycle DRAMs. This serves to optimize the memory bandwidth available for the read and the write operations by avoiding consecutive accesses to the same memory bank and by minimizing dead cycles. The arbiter first divides DRAM accesses into write accesses and read accesses. The access requests are divided into accesses per memory bank with a threshold limit imposed on the number of accesses to each memory bank. The write receive packets are rotated among the banks based on the write queue status. The status of the write queue for each memory bank may also be used for system flow control. The arbiter also typically includes the ability to determine access windows based on the status of the command queues, and to perform arbitration on each access window.

摘要翻译： 访问仲裁器被用于将对DRAM存储器件，特别是快速循环DRAM中的各个存储体的读取和写入访问请求进行优先级排序。 这用于通过避免对同一存储体的连续访问并且通过最小化死循环来优化用于读取和写入操作的存储器带宽。 仲裁器首先将DRAM访问划分为写访问和读访问。 访问请求被划分为每个存储体的访问，并且对每个存储体的访问次数施加了阈值限制。 基于写入队列状态，写入接收数据包在存储体之间旋转。 每个存储体的写入队列的状态也可以用于系统流控制。 仲裁器还通常包括基于命令队列的状态来确定访问窗口的能力，并且在每个访问窗口上执行仲裁。

公开(公告)号：US20060190613A1

公开(公告)日：2006-08-24

申请号：US11063950

申请日：2005-02-23

申请人： Everett Corl ,  Gordon Davis ,  Clark Jeffries ,  Steven Perrin ,  Hiroshi Takada ,  Victoria Thio

发明人： Everett Corl ,  Gordon Davis ,  Clark Jeffries ,  Steven Perrin ,  Hiroshi Takada ,  Victoria Thio

IPC分类号： G06F15/16

CPC分类号： H04L29/12009 ,  H04L29/12462 ,  H04L29/12481 ,  H04L45/745 ,  H04L61/255 ,  H04L61/2557

摘要： A method for increasing the capacity of a connection table in a firewall accelerator by means of mapping packets in one session with some common security actions into one table entry. For each of five Network Address Translation (NAT) configurations, a hash function is specified. The hash function takes into account which of four possible arrival types a packet at a firewall accelerator may have. When different arrival types of packets in the same session are processed, two or more arrival types may have the same hash value.

摘要翻译： 一种通过将一个会话中的分组映射到一个表条目中的一些常见安全措施来增加防火墙加速器中连接表的容量的方法。 对于五种网络地址转换（NAT）配置中的每一种，都指定了一个散列函数。 散列函数考虑了防火墙加速器可能具有的四个可能的到达类型中的哪一个。 当处理相同会话中的不同到达类型的分组时，两个或多个到达类型可以具有相同的哈希值。

公开(公告)号：US20060265552A1

公开(公告)日：2006-11-23

申请号：US11131582

申请日：2005-05-18

申请人： Gordon Davis ,  Thomas Genduso ,  Harold Kossman ,  Robert Todd

发明人： Gordon Davis ,  Thomas Genduso ,  Harold Kossman ,  Robert Todd

IPC分类号： G06F13/00

CPC分类号： G06F12/0862 ,  G06F12/10 ,  G06F12/1027 ,  G06F2212/6024 ,  G06F2212/6026

摘要： A prefetch mechanism using prefetch attributes is disclosed. In one aspect, an explicit request for data stored in a memory is provided, and a prefetch attribute in a page table entry associated with the explicit request is examined to determine whether to provide one or more prefetch requests based on the prefetch attribute. Another aspect includes determining dynamic prefetch attributes for use in prefetching data, in which prefetch attributes are adjusted based on memory access requests that target next sequential blocks of memory relative to the most recent previous access in a page of memory.

摘要翻译： 公开了一种使用预取属性的预取机制。 在一个方面，提供对存储在存储器中的数据的显式请求，并且检查与显式请求相关联的页表条目中的预取属性，以基于预取属性来确定是否提供一个或多个预取请求。 另一方面包括确定用于在预取数据中使用的动态预取属性，其中基于存储器访问请求来调整预取属性，所述存储器访问请求相对于存储器页面中最近的先前存取的下一个顺序存储块。

公开(公告)号：US20060039457A1

公开(公告)日：2006-02-23

申请号：US11237001

申请日：2005-09-28

申请人： Gordon Davis ,  Jeffrey Derby ,  Evangelos Eleftheriou ,  Sedat Oelcer ,  Malcolm Ware

发明人： Gordon Davis ,  Jeffrey Derby ,  Evangelos Eleftheriou ,  Sedat Oelcer ,  Malcolm Ware

IPC分类号： H04B1/38

CPC分类号： H04L25/028 ,  H04L27/2626 ,  H04M11/062 ,  Y02D50/44

摘要： A low power DSL modem transmitter, suitable for incorporation in integrated DSLAM server line cards, transmits full power physical frames which include a control channel and a data field when data is available for transmission and physical frames having only a control channel or a control channel and a low power synchronization field when data is not available for transmission. And a method for controlling the total power dissipated in the integrated DSLAM by selectively restricting the flow of data packets to the DSLs.

公开(公告)号：US20050188129A1

公开(公告)日：2005-08-25

申请号：US10783757

申请日：2004-02-20

申请人： Youseff Abdelilah ,  Bartholomew Blaner ,  Gordon Davis ,  Jeffrey Derby ,  Joseph Garvey ,  Malcolm Ware ,  Hua Ye

发明人： Youseff Abdelilah ,  Bartholomew Blaner ,  Gordon Davis ,  Jeffrey Derby ,  Joseph Garvey ,  Malcolm Ware ,  Hua Ye

IPC分类号： G06F3/00 ,  G06F13/28 ,  H04L29/06

CPC分类号： G06F13/28

摘要： A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.

摘要翻译： 一种用于促进数字间数字信号处理（DSP）数据通信的方法，计算机程序产品和系统。 直接存储器访问（DMA）控制器可以被配置为便于在耦合到DMA控制器的第一和第二DSP处理器核之间传输数据。 DMA控制器可以读取被称为“缓冲器描述符块”的数据结构来执行数据传送。 缓冲器描述符块可以存储指示要检索和存储数据的源地址和目的地址。 缓冲器描述符块还可以存储指示要传送的数据的大小的值，例如字节数。 然后，DMA控制器可以将位于第一DSP处理器核心中的源地址处的数据以从缓冲器描述符块指示的大小（例如，字节数）传送到第二DSP处理器核心中的目的地地址。