Ohmic contact for III-V semiconductor materials
    12.
    发明授权
    Ohmic contact for III-V semiconductor materials 失效
    欧姆接触III-V半导体材料

    公开(公告)号:US5430327A

    公开(公告)日:1995-07-04

    申请号:US121081

    申请日:1993-09-14

    CPC classification number: H01L23/532 H01L21/28575 H01L2924/0002 Y10S148/02

    Abstract: An ohmic contact to a III-V semiconductor material is fabricated. First, a III-V semiconductor material is provided. Source/drain regions are then formed in the III-V semiconductor material. On the III-V semiconductor material, a contact system is formed which is dry etchable using reactive ions such as chlorine or fluorine and substantially free of arsenic. Subsequently, a portion of the contact system is dry etched using reactive ions such as chlorine or fluorine to leave a portion of the contact system remaining on the source/drain regions. Then, the III-V semiconductor material and the contact system are annealed in an atmosphere substantially free of arsenic at a temperature at which at least a part of the contact system is alloyed with the source/drain regions to form an ohmic contact with the source/drain regions of the III-V semiconductor material.

    Abstract translation: 制造与III-V半导体材料的欧姆接触。 首先,提供III-V族半导体材料。 然后在III-V半导体材料中形成源/漏区。 在III-V半导体材料上,形成了使用诸如氯或氟的活性离子并且基本上不含砷的可干蚀刻的接触系统。 随后,使用诸如氯或氟的活性离子干接刻蚀接触系统的一部分,以使接触系统的一部分留在源/漏区上。 然后,III-V族半导体材料和接触系统在基本上不含砷的气氛中在至少一部分接触系统与源极/漏极区域合金化的温度下退火,以形成与源极的欧姆接触 /漏极区域。

    Method of forming an ohmic contact to III-V semiconductor materials
    13.
    发明授权
    Method of forming an ohmic contact to III-V semiconductor materials 失效
    形成与III-V半导体材料的欧姆接触的方法

    公开(公告)号:US5275971A

    公开(公告)日:1994-01-04

    申请号:US871785

    申请日:1992-04-20

    CPC classification number: H01L23/532 H01L21/28575 H01L2924/0002 Y10S148/02

    Abstract: An ohmic contact to a III-V semiconductor material is fabricated. First, a III-V semiconductor material is provided. Source/drain regions are then formed in the III-V semiconductor material. On the III-V semiconductor material, a contact system is formed which is dry etchable using reactive ions such as chlorine or fluorine and substantially free of arsenic. Subsequently, a portion of the contact system is dry etched using reactive ions such as chlorine or fluorine to leave a portion of the contact system remaining on the source/drain regions. Then, the III-V semiconductor material and the contact system are annealed in an atmosphere substantially free of arsenic at a temperature at which at least a part of the contact system is alloyed with the source/drain regions to form an ohmic contact with the source/drain regions of the III-V semiconductor material.

    Abstract translation: 制造与III-V半导体材料的欧姆接触。 首先,提供III-V族半导体材料。 然后在III-V半导体材料中形成源/漏区。 在III-V半导体材料上,形成了使用诸如氯或氟的活性离子并且基本上不含砷的可干蚀刻的接触系统。 随后,使用诸如氯或氟的活性离子干接刻蚀接触系统的一部分,以使接触系统的一部分留在源/漏区上。 然后,III-V族半导体材料和接触系统在基本上不含砷的气氛中在至少一部分接触系统与源极/漏极区域合金化的温度下退火,以形成与源极的欧姆接触 /漏极区域。

    Fabricating a low leakage current LED
    14.
    发明授权
    Fabricating a low leakage current LED 失效
    制造低漏电流LED

    公开(公告)号:US5164329A

    公开(公告)日:1992-11-17

    申请号:US767956

    申请日:1991-09-30

    Abstract: A method of reducing the leakage current of a III-V compound semiconductor device (10) includes providing the device with a confinement layer having two sections (13, 14). A first section (14) has a higher doping concentration than a second section (13). An energy barrier that confines minority carriers to an active layer (12) of the device (10) is formed by diffusing a dopant into a portion of the active layer (12) and the two sections (13, 14) of the confinement layer. During the diffusion, the conductivity type of a portion of the lower doped second section (13) is inverted while the higher doped first section (14) is not inverted.

    Abstract translation: 降低III-V族化合物半导体器件(10)的漏电流的方法包括为器件提供具有两个部分(13,14)的约束层。 第一部分(14)具有比第二部分(13)更高的掺杂浓度。 将少数载流子限制到器件(10)的有源层(12)的能量势垒通过将掺杂剂扩散到约束层的有源层(12)和两个部分(13,14)的一部分中而形成。 在扩散期间,下掺杂第二部分(13)的一部分的导电类型被反转,而较高掺杂的第一部分(14)不反转。

    Method for making a self-aligned impurity induced disordered structure
    15.
    发明授权
    Method for making a self-aligned impurity induced disordered structure 失效
    使自对准杂质引起无序结构的方法

    公开(公告)号:US5061656A

    公开(公告)日:1991-10-29

    申请号:US618552

    申请日:1990-11-27

    CPC classification number: H01L33/44 H01L33/0062 H01L33/30 Y10S148/031

    Abstract: A method for making a self-aligned IID structure for an LED (10) is provided. This self-aligned IID structure is accomplished by depositing a dopant layer (17) over the LED structure. A polymeric material is deposited over layer (17). The polymeric layer and dopant containing layer (17) are etched to a predetermined position. The remaining polymeric material is removed from the LED (10) structure. The LED (10) structure is annealed to produce an IID structure by laterally diffusing dopants from layer (17) into at least one side wall of the LED (10).

    Abstract translation: 提供了一种用于制造用于LED(10)的自对准IID结构的方法。 这种自对准IID结构通过在LED结构上沉积掺杂剂层(17)来实现。 聚合物材料沉积在层(17)上。 将聚合物层和掺杂剂层(17)蚀刻到预定位置。 剩余的聚合物材料从LED(10)结构中去除。 通过将掺杂剂从层(17)横向扩散到LED(10)的至少一个侧壁中,将LED(10)结构退火以产生IID结构。

    Self aligned, substrate emitting LED
    16.
    发明授权
    Self aligned, substrate emitting LED 失效
    自对准,衬底发射LED

    公开(公告)号:US4989050A

    公开(公告)日:1991-01-29

    申请号:US399049

    申请日:1989-08-28

    CPC classification number: H01L33/38 H01L33/0025 H01L33/0062

    Abstract: A light emitting diode is provided comprising a substrate which is transparent to the emitted light upon which a plurality of semiconductor layers, including a quantum well active layer, are formed. The materials are chosen not only for their optical characteristics but also so that many of the layers act as etch stops for layers which are formed on top of them. In addition to operational semiconductor layes which form the light emitting diode, two sacrificial semiconductor layers are formed on the substrate which serve as masks during processing and are removed prior to device metallization. An initial pattern is formed in the uppermost semiconductor layer and is transferred down through lower layers using the etch stop layers and selective etches so that further photolithography steps are unnecessary. Electrodes are formed on one side of the device by conventional metal deposition techniques and are self aligned to the LED junction.

    Abstract translation: 提供了一种发光二极管,其包括对发射的光透明的衬底,在衬底上形成包括量子阱活性层的多个半导体层。 这些材料不仅用于其光学特性,而且还使得许多层用作形成在它们之上的层的蚀刻停止。 除了形成发光二极管的操作半导体层之外,在衬底上形成两个牺牲半导体层,其在处理期间用作掩模,并且在器件金属化之前被去除。 在最上半导体层中形成初始图案,并且通过使用蚀刻停止层和选择性蚀刻的下层向下传送,使得不需要进一步的光刻步骤。 电极通过常规的金属沉积技术形成在器件的一侧,并且与LED结自对准。

    Field emission display having an offset phosphor and method for the operation thereof
    20.
    发明授权
    Field emission display having an offset phosphor and method for the operation thereof 失效
    具有偏移荧光体的场发射显示器及其操作方法

    公开(公告)号:US06225761B1

    公开(公告)日:2001-05-01

    申请号:US09406410

    申请日:1999-09-27

    CPC classification number: H01J29/484 H01J29/46 H01J29/84 H01J31/127

    Abstract: A field emission display (100, 200, 300) includes a plurality of offset phosphors (126) and a cathode plate (110). Cathode plate (110) has a plurality of non-electron-emissive structures (112), a plurality of electron-emissive pixels (108), and a plurality of focusing electrodes (106). Offset phosphors (126) are aligned one each with non-electron-emissive structures (112) of cathode plate (110). Focusing electrodes (106) are disposed to cause a plurality of emission currents (134), which are generated by electron-emissive pixels (108), to be directed one each toward offset phosphors (126). Ions liberated from offset phosphors (126) are received by non-electron-emissive structures (112) of cathode plate (110), thereby ameliorating ion bombardment of electron-emissive pixels (108).

    Abstract translation: 场发射显示器(100,200,300)包括多个偏移荧光体(126)和阴极板(110)。 阴极板(110)具有多个非电子发射结构(112),多个电子发射像素(108)和多个聚焦电极(106)。 偏置荧光体(126)各自具有阴极板(110)的非电子发射结构(112)。 设置聚焦电极(106)以使由电子发射像素(108)产生的多个发射电流(134)被引导到偏移的磷光体(126)。 从偏移荧光体(126)释放的离子由阴极板(110)的非电子发射结构(112)接收,从而改善电子发射像素(108)的离子轰击。

Patent Agency Ranking