Abstract:
A field emission display includes an insulating layer and an emitting layer disposed on the faceplate. A vacuum chamber is disposed between a backplane and the emitting layer and contains a getter. Apertures are defined through the insulating layer and the emitting layer for communicating contaminates from the faceplate to the vacuum chamber.
Abstract:
An ohmic contact to a III-V semiconductor material is fabricated. First, a III-V semiconductor material is provided. Source/drain regions are then formed in the III-V semiconductor material. On the III-V semiconductor material, a contact system is formed which is dry etchable using reactive ions such as chlorine or fluorine and substantially free of arsenic. Subsequently, a portion of the contact system is dry etched using reactive ions such as chlorine or fluorine to leave a portion of the contact system remaining on the source/drain regions. Then, the III-V semiconductor material and the contact system are annealed in an atmosphere substantially free of arsenic at a temperature at which at least a part of the contact system is alloyed with the source/drain regions to form an ohmic contact with the source/drain regions of the III-V semiconductor material.
Abstract:
An ohmic contact to a III-V semiconductor material is fabricated. First, a III-V semiconductor material is provided. Source/drain regions are then formed in the III-V semiconductor material. On the III-V semiconductor material, a contact system is formed which is dry etchable using reactive ions such as chlorine or fluorine and substantially free of arsenic. Subsequently, a portion of the contact system is dry etched using reactive ions such as chlorine or fluorine to leave a portion of the contact system remaining on the source/drain regions. Then, the III-V semiconductor material and the contact system are annealed in an atmosphere substantially free of arsenic at a temperature at which at least a part of the contact system is alloyed with the source/drain regions to form an ohmic contact with the source/drain regions of the III-V semiconductor material.
Abstract:
A method of reducing the leakage current of a III-V compound semiconductor device (10) includes providing the device with a confinement layer having two sections (13, 14). A first section (14) has a higher doping concentration than a second section (13). An energy barrier that confines minority carriers to an active layer (12) of the device (10) is formed by diffusing a dopant into a portion of the active layer (12) and the two sections (13, 14) of the confinement layer. During the diffusion, the conductivity type of a portion of the lower doped second section (13) is inverted while the higher doped first section (14) is not inverted.
Abstract:
A method for making a self-aligned IID structure for an LED (10) is provided. This self-aligned IID structure is accomplished by depositing a dopant layer (17) over the LED structure. A polymeric material is deposited over layer (17). The polymeric layer and dopant containing layer (17) are etched to a predetermined position. The remaining polymeric material is removed from the LED (10) structure. The LED (10) structure is annealed to produce an IID structure by laterally diffusing dopants from layer (17) into at least one side wall of the LED (10).
Abstract:
A light emitting diode is provided comprising a substrate which is transparent to the emitted light upon which a plurality of semiconductor layers, including a quantum well active layer, are formed. The materials are chosen not only for their optical characteristics but also so that many of the layers act as etch stops for layers which are formed on top of them. In addition to operational semiconductor layes which form the light emitting diode, two sacrificial semiconductor layers are formed on the substrate which serve as masks during processing and are removed prior to device metallization. An initial pattern is formed in the uppermost semiconductor layer and is transferred down through lower layers using the etch stop layers and selective etches so that further photolithography steps are unnecessary. Electrodes are formed on one side of the device by conventional metal deposition techniques and are self aligned to the LED junction.
Abstract:
The present invention provides devices and methods for testing the electrical performance of thin-film transistor backplane arrays and protecting thin-films during testing and handling.
Abstract:
The present invention provides devices capable of testing the electrical performance of thin-film transistor backplane arrays and methods for their use.
Abstract:
The present invention provides devices and methods for testing the electrical performance of thin-film transistor backplane arrays and protecting thin-films during testing and handling.
Abstract:
A field emission display (100, 200, 300) includes a plurality of offset phosphors (126) and a cathode plate (110). Cathode plate (110) has a plurality of non-electron-emissive structures (112), a plurality of electron-emissive pixels (108), and a plurality of focusing electrodes (106). Offset phosphors (126) are aligned one each with non-electron-emissive structures (112) of cathode plate (110). Focusing electrodes (106) are disposed to cause a plurality of emission currents (134), which are generated by electron-emissive pixels (108), to be directed one each toward offset phosphors (126). Ions liberated from offset phosphors (126) are received by non-electron-emissive structures (112) of cathode plate (110), thereby ameliorating ion bombardment of electron-emissive pixels (108).