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公开(公告)号：US20200349326A1
公开(公告)日：2020-11-05
申请号：US16934790
申请日：2020-07-21
Applicant: D-WAVE SYSTEMS INC.
Inventor： Andrew Douglas King
Abstract: In a hybrid computing system including at least one analog processor and at least one digital processor an embedded problem is repeatedly run or executed on the analog processor(s) to generate a first plurality of candidate solutions to the computational problem, the candidate solutions are returned to the digital processor(s) which determine a value for at least one statistical feature of the candidate solutions, at least one programmable parameter of the plurality of analog devices in the analog processor(s) is adjusted to at least partially compensate for deviations from an expected value of the at least one statistical feature, the expected value of the at least one statistical feature inferred from the structure of the embedded problem, the embedded problem is again repeatedly run or executed on the analog processor(s) to generate a second plurality of candidate solutions to the computational problem.
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公开(公告)号：US20200320424A1
公开(公告)日：2020-10-08
申请号：US16858108
申请日：2020-04-24
Applicant: D-WAVE SYSTEMS INC.
Inventor： Sheir Yarkoni , Trevor Michael Lanting , Kelly T. R. Boothby , Andrew Douglas King , Evgeny A. Andriyash , Mohammad H. Amin
Abstract: A computational method via a hybrid processor comprising an analog processor and a digital processor includes determining a first classical spin configuration via the digital processor, determining preparatory biases toward the first classical spin configuration, programming an Ising problem and the preparatory biases in the analog processor via the digital processor, evolving the analog processor in a first direction, latching the state of the analog processor for a first dwell time, programming the analog processor to remove the preparatory biases via the digital processor, determining a tunneling energy via the digital processor, determining a second dwell time via the digital processor, evolving the analog processor in a second direction until the analog processor reaches the tunneling energy, and evolving the analog processor in the first direction until the analog processor reaches a second classical spin configuration.
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公开(公告)号：US09875444B2
公开(公告)日：2018-01-23
申请号：US15373910
申请日：2016-12-09
Applicant: D-Wave Systems Inc.
Inventor： Andrew Douglas King
IPC: G06N99/00 , G06F15/76 , H03K19/195
CPC classification number: G06N99/002 , G06F15/76 , H03K19/195
Abstract: A problem graph having one or more odd cycles is embedded in a quantum processor. The quantum processor includes a plurality of qubits and coupling devices, each coupling device operable to provide controllable communicative coupling between a respective pair of the plurality of qubits to form an interconnected topology. Embedding may, for example, be realized by mapping each vertex of the problem graph to a respective single qubit; mapping each edge of the problem graph to a respective single coupling device, where for pairs of qubits, each qubit of the pair is mapped to a respective pair of vertices. The problem graph may include one or more sub-graphs, one or more of the sub-graphs being a bipartite K3,3 graph.
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公开(公告)号：US20170255872A1
公开(公告)日：2017-09-07
申请号：US15505522
申请日：2015-08-21
Applicant: D-Wave Systems Inc.
Inventor： Firas Hamze , Andrew Douglas King , Jack Raymond , Aidan Patrick Roy , Robert Israel , Evgeny Andriyash , Catherine McGeoch , Mani Ranjbar
CPC classification number: G06N99/002 , G06F9/02 , G06F9/32 , G06F15/18 , G06F15/76 , G06F17/10 , G06N3/12
Abstract: Computational systems implement problem solving using heuristic solvers or optimizers. Such may iteratively evaluate a result of processing, and modify the problem or representation thereof before repeating processing on the modified problem, until a termination condition is reached. Heuristic solvers or optimizers may execute on one or more digital processors and/or one or more quantum processors. The system may autonomously select between types of hardware devices and/or types of heuristic optimization algorithms. Such may coordinate or at least partially overlap post-processing operations with processing operations, for instance performing post-processing on an ith batch of samples while generating an (i+1)th batch of samples, e.g., so post-processing operation on the ith batch of samples does not extend in time beyond the generation of the (i+1)th batch of samples. Heuristic optimizers selection is based on pre-processing assessment of the problem, e.g., based on features extracted from the problem and for instance, on predicted success.
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公开(公告)号：US20170220510A1
公开(公告)日：2017-08-03
申请号：US15418497
申请日：2017-01-27
Applicant: D-Wave Systems Inc.
Inventor： Jeremy P. Hilton , Aidan Patrick Roy , Paul I. Bunyk , Andrew Douglas King , Tomas J. Boothby , Richard G. Harris , Chunqing Deng
CPC classification number: G06F13/4068 , G06F13/36 , G06N99/002
Abstract: Topologies for analog computing systems are provided. Qubits in the topology are grouped into cells, and cells are coupled to adjacent cells by inter-cell couplers. At least some cells are coupled to non-adjacent cells via long-range couplers. Long-range couplers may be arranged into coverings so that certain sets of qubits within a covering region may be coupled with a reduced number of couplers. Each cell within a covering region without a long-range coupler may be proximate to a cell with a long range coupler so that each cell within the covering region is no more than a certain coupling distance away from a long-range coupler. Long-range couplers may couple over a greater physical distance than inter-cell couplers. Long-range couplers may couple to qubits over a larger coupling region, and may extend across multiple crossing regions between qubits.
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Patent Agency Ranking
公开(公告)号：US11900185B2
公开(公告)日：2024-02-13
申请号：US16934790
申请日：2020-07-21
Applicant: D-WAVE SYSTEMS INC.
Inventor： Andrew Douglas King
CPC classification number: G06J1/00 , A61K31/496 , A61K45/06 , G06N3/063 , G06N5/04 , G06N10/00 , A61N5/062 , A61N5/10
Abstract: In a hybrid computing system including at least one analog processor and at least one digital processor an embedded problem is repeatedly run or executed on the analog processor(s) to generate a first plurality of candidate solutions to the computational problem, the candidate solutions are returned to the digital processor(s) which determine a value for at least one statistical feature of the candidate solutions, at least one programmable parameter of the plurality of analog devices in the analog processor(s) is adjusted to at least partially compensate for deviations from an expected value of the at least one statistical feature, the expected value of the at least one statistical feature inferred from the structure of the embedded problem, the embedded problem is again repeatedly run or executed on the analog processor(s) to generate a second plurality of candidate solutions to the computational problem.
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公开(公告)号：US11861455B2
公开(公告)日：2024-01-02
申请号：US16858108
申请日：2020-04-24
Applicant: D-WAVE SYSTEMS INC.
Inventor： Sheir Yarkoni , Trevor Michael Lanting , Kelly T. R. Boothby , Andrew Douglas King , Evgeny A. Andriyash , Mohammad H. Amin
Abstract: A computational method via a hybrid processor comprising an analog processor and a digital processor includes determining a first classical spin configuration via the digital processor, determining preparatory biases toward the first classical spin configuration, programming an Ising problem and the preparatory biases in the analog processor via the digital processor, evolving the analog processor in a first direction, latching the state of the analog processor for a first dwell time, programming the analog processor to remove the preparatory biases via the digital processor, determining a tunneling energy via the digital processor, determining a second dwell time via the digital processor, evolving the analog processor in a second direction until the analog processor reaches the tunneling energy, and evolving the analog processor in the first direction until the analog processor reaches a second classical spin configuration.
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公开(公告)号：US10671937B2
公开(公告)日：2020-06-02
申请号：US16308314
申请日：2017-06-07
Applicant: Sheir Yarkoni , D-WAVE SYSTEMS INC.
Inventor： Sheir Yarkoni , Trevor Michael Lanting , Kelly T. R. Boothby , Andrew Douglas King , Evgeny A. Andriyash , Mohammad H. Amin
Abstract: A computational method via a hybrid processor comprising an analog processor and a digital processor includes determining a first classical spin configuration via the digital processor, determining preparatory biases toward the first classical spin configuration, programming an Ising problem and the preparatory biases in the analog processor via the digital processor, evolving the analog processor in a first direction, latching the state of the analog processor for a first dwell time, programming the analog processor to remove the preparatory biases via the digital processor, determining a tunneling energy via the digital processor, determining a second dwell time via the digital processor, evolving the analog processor in a second direction until the analog processor reaches the tunneling energy, and evolving the analog processor in the first direction until the analog processor reaches a second classical spin configuration.
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公开(公告)号：US20190266510A1
公开(公告)日：2019-08-29
申请号：US16308314
申请日：2017-06-07
Applicant: Sheir YARKONI , D-WAVE SYSTEMS INC.
Inventor： Sheir Yarkoni , Trevor Michael Lanting , Kelly T. R. Boothby , Andrew Douglas King , Evgeny A. Andriyash , Mohammad H. Amin
Abstract: A hybrid computer for generating samples employs a digital computer operable to perform post-processing. An analog computer may be communicatively coupled to the digital computer. The analog computer may be operable to return one or more samples corresponding to low-energy configurations of a Hamiltonian. Methods of generating samples from a quantum Boltzmann distribution to train a Quantum Boltzmann Machine, and from a classical Boltzmann distribution to train a Restricted Boltzmann Machine, are also taught. Computational systems and methods permit processing problems having size and/or connectivity greater than, and/or at least not fully provided by, a working graph of an analog processor. The approach may include determining preparatory biases toward a first classical spin configuration, evolving the analog processor in a first direction; evolving the analog processor in a second direction and evolving the analog processor in the first direction until the analog processor reaches a second classical spin configuration.
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公开(公告)号：US20180246848A1
公开(公告)日：2018-08-30
申请号：US15549512
申请日：2016-01-27
Applicant: D-Wave Systems Inc.
Inventor： Adam Douglass , Richard G. Harris , Trevor Michael Lanting , Andrew Douglas King , Jack Raymond , Murray C. Thom
CPC classification number: G06F15/803 , G06N10/00
Abstract: A topology or hardware graph of a quantum processor is modifiable, for example prior to embedding of a problem, for instance by creating chains of qubits, where each chain which operates as a single or logical qubit to impose a logical graph on the quantum processor. A user interface (UI) allows a user to select a topology suited for embedding a particular problem or type of problem, to supply parameters that define the desired topology, or to supply or specify a problem graph or problem definition from which a processor-based system determines or selects an appropriate topology or logical graph to impose. Topologies may have regularity and/or self-similarity over the quantum processor or portions thereof, which portions may constitute unit cells. Logical graphs imposed on the quantum processor may take the form of a hypercube graph. A UI allows the user to specify a desired dimension of the hypercube graph.
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