公开(公告)号：US07139292B1

公开(公告)日：2006-11-21

申请号：US09943947

申请日：2001-08-31

申请人： Brian P. Evans ,  Jeffery Scott Hunt

发明人： Brian P. Evans ,  Jeffery Scott Hunt

IPC分类号： H04J3/02

CPC分类号： H03K19/17736 ,  H03K19/1737

摘要： An apparatus comprising a distributed multiplexer configured to receive a distributed input group of signals. The distributed multiplexer may be configured to evenly load the distributed input groups.

摘要翻译： 一种包括被配置为接收分布式输入信号组的分布式多路复用器的装置。 分布式多路复用器可以被配置为均匀地加载分布式输入组。

公开(公告)号：US06801064B1

公开(公告)日：2004-10-05

申请号：US10228436

申请日：2002-08-27

申请人： Jeffery Scott Hunt ,  Scott Anthony Jackson

发明人： Jeffery Scott Hunt ,  Scott Anthony Jackson

IPC分类号： H03B100

CPC分类号： H03K19/018521 ,  H03K19/0013 ,  H03K19/00315

摘要： A buffer includes a pull-up level shifter coupled to an input signal. A pull-down level shifter separate from the pull-up level shifter is coupled to the input signal. A driver is coupled to the pull-up level shifter and the pull-down level shifter.

摘要翻译： 缓冲器包括耦合到输入信号的上拉电平移位器。 与上拉电平移位器分离的下拉电平移位器耦合到输入信号。 驱动器耦合到上拉电平移位器和下拉电平移位器。

公开(公告)号：US06490712B1

公开(公告)日：2002-12-03

申请号：US09684159

申请日：2000-10-04

申请人： James Daniel Merchant ,  Gordon Carskadon ,  Brian P. Evans ,  Jeffery Scott Hunt ,  Anup Nayak ,  Andrew Wright

发明人： James Daniel Merchant ,  Gordon Carskadon ,  Brian P. Evans ,  Jeffery Scott Hunt ,  Anup Nayak ,  Andrew Wright

IPC分类号： G06F1750

CPC分类号： G06F17/5054

摘要： A method and system for automatically identifying configuration cell addresses in a schematic hierarchy is disclosed. In one embodiment of the present invention, a memory cell (e.g., a configuration bit) is identified in a schematic hierarchy. Next, this embodiment determines an address for the memory cell. Then, this embodiment determines a unique name for the memory cell. The name is comprised of a hierarchical logical name and a schematic path name. By traversing the schematic and using logical names, all addresses of configuration bits of a circuit design may be automatically determined. The process is repeated for each memory cell in the schematic. This embodiment stores the unique name of the configuration bit and the address of the configuration bit in a data structure.

摘要翻译： 公开了用于自动识别示意图层次结构中的配置单元地址的方法和系统。 在本发明的一个实施例中，以示意性层次来识别存储器单元（例如，配置位）。 接下来，本实施例确定存储单元的地址。 然后，本实施例确定存储单元的唯一名称。 该名称由分层逻辑名称和示意图路径名称组成。 通过遍历原理图并使用逻辑名称，可以自动确定电路设计的配置位的所有地址。 在原理图中为每个存储单元重复该过程。 该实施例将配置位的唯一名称和配置位的地址存储在数据结构中。

公开(公告)号：US5774413A

公开(公告)日：1998-06-30

申请号：US764329

申请日：1996-12-12

申请人： Jeffery Scott Hunt

发明人： Jeffery Scott Hunt

IPC分类号： G11C8/12 ,  G11C8/14 ,  G11C8/00

CPC分类号： G11C8/14 ,  G11C8/12

摘要： The present invention concerns a method and apparatus for generating a global wordline signal without requiring a metal layer for the global wordline route across multiple arrays. The global wordline signal is generally cascaded between the various group arrays. A low voltage level is generally presented across the wordlines to the various arrays that are inactive to minimize the overall amount of current used by the circuit. Once a particular array is activated, the present invention boosts the signal to a high level which represents an active wordline for a selected array. The present invention uses a global wordline scheme that uses the local wordlines from the previous array to determine whether to bring the next array up to an active level.

摘要翻译： 本发明涉及一种用于生成全局字线信号而不需要跨多个阵列的全局字线路由的金属层的方法和装置。 全局字线信号通常在各种组阵列之间进行级联。 通常在字线之间呈现低电平电平到不活动的各种阵列，以最小化电路使用的电流总量。 一旦特定的阵列被激活，本发明将信号升高到代表所选阵列的有效字线的高电平。 本发明使用全局字线方案，其使用来自先前阵列的本地字线来确定是否使下一个阵列达到活动电平。

公开(公告)号：US5751644A

公开(公告)日：1998-05-12

申请号：US756634

申请日：1996-11-26

申请人： George M. Ansel ,  Jeffery Scott Hunt ,  Ping Wu ,  David A. Lindley ,  Andrew L. Hawkins

发明人： George M. Ansel ,  Jeffery Scott Hunt ,  Ping Wu ,  David A. Lindley ,  Andrew L. Hawkins

IPC分类号： B01F7/00 ,  G11C11/407

CPC分类号： G11C7/1087 ,  G11C7/1093 ,  G11C7/1096

摘要： The present invention concerns data transition method and apparatus for driving a set of write data signals to an inactive (or deasserted) state upon completion of a WRITE to a particular group of memory cells. The present invention drives the write data signals to a an inactive state to end a WRITE without waiting for the end of the write control pulse. The present invention triggers a group of data write buffers to drive one of the write data signals to a "0" at the beginning of the WRITE control pulse or at a data input transition during a WRITE. A delayed transition of the write data signals may be used to drive both the write data signals to a "1"� to end the WRITE within a particular memory group. The write data transition detection is accomplished at the write data inputs of the groups of memory cells without relying on global chip data input pin transition detection and pulse width setting. The data setup to the end of WRITE is generally not compromised since the path from chip data input to the input to the write data signals is generally similar to existing implementations.

摘要翻译： 本发明涉及数据转换方法和装置，用于在完成对特定组存储器单元的写入时将一组写入数据信号驱动到无效（或无效）状态。 本发明将写入数据信号驱动到非活动状态以结束写入而不等待写入控制脉冲的结束。 本发明触发一组数据写入缓冲器，以在WRITE控制脉冲开始时或写入期间的数据输入转换时将写数据信号之一驱动为“0”。 可以使用写入数据信号的延迟转换来将写入数据信号驱动为“1”|以结束特定存储器组中的写入。 在不依赖于全局芯片数据输入引脚转换检测和脉冲宽度设置的情况下，在存储器单元组的写入数据输入端实现写入数据转换检测。 由于从芯片数据输入到输入到写入数据信号的路径通常与现有实现相似，因此通常不会影响写入结束的数据设置。

公开(公告)号：US5737612A

公开(公告)日：1998-04-07

申请号：US316121

申请日：1994-09-30

申请人： George M. Ansel ,  Jeffery Scott Hunt ,  Christopher W. Jones ,  Jeffery Mark Marshall ,  Hatem Yazbek

发明人： George M. Ansel ,  Jeffery Scott Hunt ,  Christopher W. Jones ,  Jeffery Mark Marshall ,  Hatem Yazbek

IPC分类号： G06F1/24 ,  G06F1/30

CPC分类号： G06F1/24

摘要： A power-on reset control circuit and associated method for deactivating a global power-on-reset signal based on whether circuitry, critical to correct functionality of an electronic system employing the power-on reset, is functioning correctly. The power-on reset control circuit comprises a control emulation circuit for transmitting a control signal through a first control line to indicate that the circuitry is operating correctly. The power-on reset control circuit further comprises a control verification circuit, coupled to the control emulation circuit through the first control line, for deactivating the global power-on reset signal upon receiving an active local power-on reset signal indicating that the power source is providing a voltage at an operating threshold level and the active control signal from the control emulation circuit.

公开(公告)号：US07808275B1

公开(公告)日：2010-10-05

申请号：US11757905

申请日：2007-06-04

申请人： George McCollough Ansel ,  Jeffery Scott Hunt ,  Anand Kumar Chamakura

发明人： George McCollough Ansel ,  Jeffery Scott Hunt ,  Anand Kumar Chamakura

IPC分类号： H03K19/0175 ,  H03K19/094 ,  H03L5/00

CPC分类号： H03K19/00384 ,  H03K19/018521

摘要： Disclosed is a circuit comprising an inverter circuit which comprises inverters and level shifters; and a modulation circuit comprising a pull-up circuit and a pull-down circuit, the modulation circuit coupled to the inverter circuit to regulate the response of the circuit to an input voltage for various power supply voltage levels by the pull-up or pull-down circuit. Other embodiments are also disclosed.

摘要翻译： 公开了一种包括逆变器电路的电路，其包括逆变器和电平移位器; 以及包括上拉电路和下拉电路的调制电路，所述调制电路耦合到所述逆变器电路，以通过所述上拉或下拉电路来调节所述电路对于各种电源电压电平的输入电压的响应， 下电路。 还公开了其他实施例。

公开(公告)号：US07132854B1

公开(公告)日：2006-11-07

申请号：US10949537

申请日：2004-09-23

申请人： Suwei Chen ,  Sanjay Sancheti ,  Jeffery Scott Hunt

发明人： Suwei Chen ,  Sanjay Sancheti ,  Jeffery Scott Hunt

IPC分类号： H03K19/173 ,  H03K3/289

CPC分类号： G11C7/1045 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1072 ,  H03K19/1737

摘要： A data path (200) can be configured to accommodate different clocking arrangements. In one mode, data values may be output at a single data rate: one data value every clock cycle. In another mode, data values may be output at a double data rate: two data values every clock cycle. A data path (200) can be compact circuit structure, needing only an additional mode multiplexer (206) and inverter over a conventional D-type master-slave flip-flop.

摘要翻译： 数据路径（200）可被配置为适应不同的时钟配置。 在一种模式中，数据值可以以单个数据速率输出：每个时钟周期一个数据值。 在另一种模式下，数据值可以以双倍数据速率输出：每个时钟周期两个数据值。 数据路径（200）可以是紧凑的电路结构，仅需要通过常规D型主从触发器的附加模式多路复用器（206）和反相器。

公开(公告)号：US06904436B1

公开(公告)日：2005-06-07

申请号：US09684160

申请日：2000-10-04

申请人： James Daniel Merchant ,  Gordon Carskadon ,  Brian P. Evans ,  Jeffery Scott Hunt ,  Anup Nayak ,  Andrew Wright

发明人： James Daniel Merchant ,  Gordon Carskadon ,  Brian P. Evans ,  Jeffery Scott Hunt ,  Anup Nayak ,  Andrew Wright

IPC分类号： G06F7/08 ,  G06F17/50

CPC分类号： G06F17/5054 ,  Y10S707/956 ,  Y10S707/99942

摘要： A method and system for automatically building a bit order data structure of configuration bits for a programmable logic device. One embodiment of the present invention first identifies a plurality of memory cells in a hierarchical schematic representation of the programmable device. Next, this embodiment determines a plurality of addresses corresponding to the plurality of memory cells. This embodiment next determines a plurality of logical names for the plurality of memory cells. Then, based on an order in which the plurality of addresses are to be loaded into the programmable logic device, this embodiment orders the plurality of logical names for the plurality of memory cells. Another embodiment first accesses a database comprising a plurality of logical names corresponding to a plurality of addresses. Then, this embodiment accesses a database specifying an order in which the plurality of addresses are to be loaded into the programmable logic device. Next, this embodiment orders the plurality of logical names based on the order specified in the database from the previous step.

摘要翻译： 一种用于自动构建可编程逻辑器件的配置位的位顺序数据结构的方法和系统。 本发明的一个实施例首先以可编程设备的分层示意图表示识别多个存储器单元。 接下来，本实施例确定与多个存储单元对应的多个地址。 该实施例接下来确定多个存储单元的多个逻辑名称。 然后，基于将多个地址加载到可编程逻辑器件中的顺序，本实施例对多个存储器单元定义多个逻辑名称。 另一个实施例首先访问包括与多个地址对应的多个逻辑名称的数据库。 然后，本实施例访问指定将多个地址加载到可编程逻辑器件中的顺序的数据库。 接下来，本实施例基于从前一步骤在数据库中指定的顺序来订购多个逻辑名称。

公开(公告)号：US06815984B1

公开(公告)日：2004-11-09

申请号：US09940406

申请日：2001-08-27

申请人： Benjamin J. Bowers ,  Brian P. Evans ,  Jeffery Scott Hunt

发明人： Benjamin J. Bowers ,  Brian P. Evans ,  Jeffery Scott Hunt

IPC分类号： H03B103

CPC分类号： H03K19/09429

摘要： An apparatus comprising an input section and an output section. The input section may be configured to generate a first control signal and a second control signal in response to an input signal and a select signal. The output section may be configured to generate an output signal in response to the first and second control signals. The output signal may be (i) related to the input signal when in a first mode and (ii) disabled when in a second mode.

摘要翻译： 一种包括输入部分和输出部分的装置。 输入部分可以被配置为响应于输入信号和选择信号而产生第一控制信号和第二控制信号。 输出部分可以被配置为响应于第一和第二控制信号而产生输出信号。 输出信号可以是（i）当处于第一模式时与输入信号相关，并且（ii）当处于第二模式时被禁止。