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32 条记录 (耗时 0.025 秒)

    Data transition detect write control
    1.
    发明授权
    Data transition detect write control 失效
    数据转换检测写入控制

    公开(公告)号：US5751644A

    公开(公告)日：1998-05-12

    申请号：US756634

    申请日：1996-11-26

    申请人： George M. Ansel ,  Jeffery Scott Hunt ,  Ping Wu ,  David A. Lindley ,  Andrew L. Hawkins

    发明人： George M. Ansel ,  Jeffery Scott Hunt ,  Ping Wu ,  David A. Lindley ,  Andrew L. Hawkins

    IPC分类号： B01F7/00 ,  G11C11/407

    CPC分类号： G11C7/1087 ,  G11C7/1093 ,  G11C7/1096

    摘要： The present invention concerns data transition method and apparatus for driving a set of write data signals to an inactive (or deasserted) state upon completion of a WRITE to a particular group of memory cells. The present invention drives the write data signals to a an inactive state to end a WRITE without waiting for the end of the write control pulse. The present invention triggers a group of data write buffers to drive one of the write data signals to a "0" at the beginning of the WRITE control pulse or at a data input transition during a WRITE. A delayed transition of the write data signals may be used to drive both the write data signals to a "1"� to end the WRITE within a particular memory group. The write data transition detection is accomplished at the write data inputs of the groups of memory cells without relying on global chip data input pin transition detection and pulse width setting. The data setup to the end of WRITE is generally not compromised since the path from chip data input to the input to the write data signals is generally similar to existing implementations.

    摘要翻译： 本发明涉及数据转换方法和装置，用于在完成对特定组存储器单元的写入时将一组写入数据信号驱动到无效（或无效）状态。 本发明将写入数据信号驱动到非活动状态以结束写入而不等待写入控制脉冲的结束。 本发明触发一组数据写入缓冲器，以在WRITE控制脉冲开始时或写入期间的数据输入转换时将写数据信号之一驱动为“0”。 可以使用写入数据信号的延迟转换来将写入数据信号驱动为“1”|以结束特定存储器组中的写入。 在不依赖于全局芯片数据输入引脚转换检测和脉冲宽度设置的情况下，在存储器单元组的写入数据输入端实现写入数据转换检测。 由于从芯片数据输入到输入到写入数据信号的路径通常与现有实现相似，因此通常不会影响写入结束的数据设置。

    Multi-port memory cell and access method
    2.
    发明授权
    Multi-port memory cell and access method 有权
    多端口存储单元和访问方式

    公开(公告)号：US07113445B1

    公开(公告)日：2006-09-26

    申请号：US10948006

    申请日：2004-09-22

    申请人： Sanjay Sancheti ,  Jeffery Scott Hunt ,  George M. Ansel

    发明人： Sanjay Sancheti ,  Jeffery Scott Hunt ,  George M. Ansel

    IPC分类号： G11C8/00

    CPC分类号： G11C11/412

    摘要： A multi-port memory cell (200) can be formed from seven transistors. Single ended write operations can be performed without a boosted word line voltage or variable power supply. A data value (D/DB) stored in the memory cell (200) can be cleared by shorting complementary data nodes (204-0 and 204-1) together. Write data can then be placed on a bit line. Complementary data nodes (204-0 and 204-1) can then be isolated once again, resulting in the write data being latched within the memory cell (300). An access method (700) for a multi-port memory cell is also described.

    摘要翻译： 多端口存储单元（200）可以由七个晶体管形成。 可以在没有增强字线电压或可变电源的情况下执行单端写操作。 存储在存储单元（200）中的数据值（D / DB）可以通过将互补数据节点（204-0和204-1）一起短路来清除。 然后可以将数据写入位线。 然后可以再次分离互补数据节点（204-0和204-1），导致写数据被锁存在存储单元（300）内。 还描述了用于多端口存储器单元的访问方法（700）。

    Power-on reset control circuit
    3.
    发明授权
    Power-on reset control circuit 失效
    上电复位控制电路

    公开(公告)号：US5809312A

    公开(公告)日：1998-09-15

    申请号：US920124

    申请日：1997-09-02

    申请人： George M. Ansel ,  Jeffery Scott Hunt ,  Christopher W. Jones ,  Jeffery Mark Marshall ,  Hatem Yazbek

    发明人： George M. Ansel ,  Jeffery Scott Hunt ,  Christopher W. Jones ,  Jeffery Mark Marshall ,  Hatem Yazbek

    IPC分类号： G06F1/24 ,  G06F1/26

    CPC分类号： G06F1/24

    摘要： A power-on reset control circuit and associated method for deactivating a global power-on-reset signal based on whether circuitry, critical to correct functionality of an electronic system employing the power-on reset, is functioning correctly. The power-on reset control circuit comprises a control emulation circuit for transmitting a control signal through a first control line to indicate that the circuitry is operating correctly. The power-on reset control circuit further comprises a control verification circuit, coupled to the control emulation circuit through the first control line, for deactivating the global power-on reset signal upon receiving an active local power-on reset signal indicating that the power source is providing a voltage at an operating threshold level and the active control signal from the control emulation circuit.

    摘要翻译： 一种上电复位控制电路和相关联的方法，用于基于对正确使用上电复位的电子系统的功能进行正确的电路电路来去激活全局上电复位信号。 上电复位控制电路包括用于通过第一控制线发送控制信号以指示电路正常工作的控制仿真电路。 上电复位控制电路还包括控制验证电路，其通过第一控制线耦合到控制仿真电路，用于在接收到指示电源的有源局部上电复位信号时去激活全局上电复位信号 提供了操作阈值电平的电压和来自控制仿真电路的有源控制信号。

    Power-on reset control circuit
    4.
    发明授权
    Power-on reset control circuit 失效

    公开(公告)号：US5737612A

    公开(公告)日：1998-04-07

    申请号：US316121

    申请日：1994-09-30

    申请人： George M. Ansel ,  Jeffery Scott Hunt ,  Christopher W. Jones ,  Jeffery Mark Marshall ,  Hatem Yazbek

    发明人： George M. Ansel ,  Jeffery Scott Hunt ,  Christopher W. Jones ,  Jeffery Mark Marshall ,  Hatem Yazbek

    IPC分类号： G06F1/24 ,  G06F1/30

    CPC分类号： G06F1/24

    摘要： A power-on reset control circuit and associated method for deactivating a global power-on-reset signal based on whether circuitry, critical to correct functionality of an electronic system employing the power-on reset, is functioning correctly. The power-on reset control circuit comprises a control emulation circuit for transmitting a control signal through a first control line to indicate that the circuitry is operating correctly. The power-on reset control circuit further comprises a control verification circuit, coupled to the control emulation circuit through the first control line, for deactivating the global power-on reset signal upon receiving an active local power-on reset signal indicating that the power source is providing a voltage at an operating threshold level and the active control signal from the control emulation circuit.

    Dual level wordline clamp for reduced memory cell current
    6.
    发明授权
    Dual level wordline clamp for reduced memory cell current 失效
    双电平字线钳位，用于减少存储单元电流

    公开(公告)号：US5936894A

    公开(公告)日：1999-08-10

    申请号：US94786

    申请日：1998-06-15

    申请人： Andrew L. Hawkins ,  Jeffery Scott Hunt ,  Satish C. Saripella ,  Sanjay Sunder

    发明人： Andrew L. Hawkins ,  Jeffery Scott Hunt ,  Satish C. Saripella ,  Sanjay Sunder

    IPC分类号： G11C8/08 ,  G11C11/418 ,  G11C16/04

    CPC分类号： G11C8/08 ,  G11C11/418

    摘要： The present invention concerns a method and apparatus for providing a dual level wordline clamp for use in a memory array. During a write operation, the clamp is at a level that ensures that a proper write margin is maintained. During a read operation, the clamp produces a lower level that reduces the overall current consumption of the circuit. During a write operation, the clamp also reduces the overall current consumption of the circuit. The present invention does not require complex reference circuits and, as a result, presents a minimal impact on die size.

    摘要翻译： 本发明涉及一种用于提供用于存储器阵列的双电平字线钳位的方法和装置。 在写操作期间，钳位处于确保保持适当写入余量的水平。 在读取操作期间，钳位器产生较低的电平，降低了电路的总体电流消耗。 在写入操作期间，钳位还降低了电路的总体电流消耗。 本发明不需要复杂的参考电路，因此对芯片尺寸的影响最小。

    Input buffer system using low voltage transistors
    8.
    发明授权
    Input buffer system using low voltage transistors 有权
    输入缓冲系统采用低压晶体管

    公开(公告)号：US06784717B1

    公开(公告)日：2004-08-31

    申请号：US10229481

    申请日：2002-08-28

    申请人： Jeffery Scott Hunt ,  Scott Anthony Jackson

    发明人： Jeffery Scott Hunt ,  Scott Anthony Jackson

    IPC分类号： H03K508

    CPC分类号： H03K5/08

    摘要： An input buffer system has an input clipping circuit. The input clipping circuit has a high voltage input and uses transistors all being the thin oxide type transistors. A high voltage detect circuit is coupled to the input clipping circuit. An input buffer circuit is coupled to the input clipping circuit and has a low voltage output range.

    摘要翻译： 输入缓冲器系统具有输入限幅电路。 输入限幅电路具有高电压输入，并且使用全部为薄氧化物型晶体管的晶体管。 高电压检测电路耦合到输入限幅电路。 输入缓冲电路耦合到输入限幅电路并且具有低电压输出范围。

    Electrical ID method for output driver
    9.
    发明授权
    Electrical ID method for output driver 有权
    输出驱动器的电气ID方法

    公开(公告)号：US06353336B1

    公开(公告)日：2002-03-05

    申请号：US09534663

    申请日：2000-03-24

    申请人： David R. Lindley ,  William G. Baker ,  Jeffery Scott Hunt

    发明人： David R. Lindley ,  William G. Baker ,  Jeffery Scott Hunt

    IPC分类号： H03K190175

    CPC分类号： G06F11/006

    摘要： An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first output signal in response to one or more first input signals. The second circuit may be configured to generate a second output signal in response to one or more second input signals. The first and second output signals may be presented to a bond pad.

    摘要翻译： 一种包括第一电路和第二电路的装置。 第一电路可以被配置为响应于一个或多个第一输入信号而产生第一输出信号。 第二电路可以被配置为响应于一个或多个第二输入信号而产生第二输出信号。 第一和第二输出信号可以被呈现给接合焊盘。

    Method, architecture and circuit for reducing and/or eliminating small signal voltage swing sensitivity
    10.
    发明授权
    Method, architecture and circuit for reducing and/or eliminating small signal voltage swing sensitivity 有权
    降低和/或消除小信号电压摆幅灵敏度的方法，架构和电路

    公开(公告)号：US5978280A

    公开(公告)日：1999-11-02

    申请号：US132100

    申请日：1998-08-10

    申请人： Satish C. Saripella ,  Jeffery Scott Hunt ,  Sudhaker Reddy Anumula ,  Ajay Srikrishna

    发明人： Satish C. Saripella ,  Jeffery Scott Hunt ,  Sudhaker Reddy Anumula ,  Ajay Srikrishna

    IPC分类号： G11C7/06 ,  G11C13/00

    CPC分类号： G11C7/06

    摘要： A circuit comprising a sense amplifier, an evaluation circuit, a control circuit and a register circuit. The sense amplifier circuit may be configured to present a first output and a second output in response to (i) an input signal and (ii) an enable signal. The evaluation circuit may be configured to present an evaluation signal in response to the first and second outputs. The control circuit may be configured to present (i) a first clock signal, a second clock signal and an enable signal in response to (i) the evaluation signal and (ii) a wordline signal. The register circuit may be configured to hold either the first or second output in response to the first and second clock signals. The register circuit may be implemented as a master-slave register that may respond to the first and second clock signals.

    摘要翻译： 一种包括读出放大器，评估电路，控制电路和寄存器电路的电路。 读出放大器电路可以被配置为响应于（i）输入信号和（ii）使能信号而呈现第一输出和第二输出。 评估电路可以被配置为响应于第一和第二输出呈现评估信号。 响应于（i）评估信号和（ii）字线信号，控制电路可以被配置为呈现（i）第一时钟信号，第二时钟信号和使能信号。 寄存器电路可以被配置为响应于第一和第二时钟信号保持第一或第二输出。 寄存器电路可以被实现为可响应于第一和第二时钟信号的主从寄存器。