公开(公告)号：US6137145A

公开(公告)日：2000-10-24

申请号：US237773

申请日：1999-01-26

申请人： Jon D. Cheek ,  Daniel Kadosh ,  Mark W. Michael

发明人： Jon D. Cheek ,  Daniel Kadosh ,  Mark W. Michael

IPC分类号： H01L21/8234 ,  H01K29/76

CPC分类号： H01L21/82345

摘要： A semiconductor topography including integrated circuit gate conductors incorporating dual polysilicon layers is provided. The semiconductor topography includes a semiconductor substrate. A first gate conductor is arranged upon a first gate dielectric and above the semiconductor substrate, and a second gate conductor is arranged upon a second gate dielectric and above the semiconductor substrate. The semiconductor substrate may contain a first active region laterally separated from a second active region by a field region. The first gate conductor may be arranged within the first active region, and the second gate conductor may be arranged within the second active region. Each gate conductor preferably includes a second polysilicon layer portion arranged upon a first polysilicon layer portion. The thicknesses of the first gate conductor and the second gate conductor are preferably equal. The first gate conductor may be doped with a first dopant that has a lower diffusion rate through polysilicon than a second dopant with which the second gate conductor is doped. The second polysilicon layer portion of the second gate conductor is substantially free of implanted dopants.

摘要翻译： 提供包括并入双多晶硅层的集成电路栅极导体的半导体形貌。 半导体形貌包括半导体衬底。 第一栅极导体布置在第一栅极电介质上并位于半导体衬底之上，并且第二栅极导体布置在第二栅极电介质上并位于半导体衬底之上。 半导体衬底可以包含通过场区域与第二有源区域横向分离的第一有源区域。 第一栅极导体可以布置在第一有源区内，并且第二栅极导体可以布置在第二有源区内。 每个栅极导体优选地包括布置在第一多晶硅层部分上的第二多晶硅层部分。 第一栅极导体和第二栅极导体的厚度优选相等。 第一栅极导体可以掺杂有第一掺杂剂，其通过多晶硅具有比掺杂第二栅极导体的第二掺杂物更低的扩散速率。 第二栅极导体的第二多晶硅层部分基本上没有注入的掺杂剂。

公开(公告)号：US06104069A

公开(公告)日：2000-08-15

申请号：US187462

申请日：1998-11-04

申请人： Michael Duane ,  Daniel Kadosh ,  Mark I. Gardner

发明人： Michael Duane ,  Daniel Kadosh ,  Mark I. Gardner

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L21/768 ,  H01L29/417 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/66568 ,  H01L21/76877 ,  H01L29/41725 ,  H01L29/41733 ,  H01L29/66575 ,  H01L29/7833 ,  H01L21/2257 ,  H01L29/665 ,  Y10S257/90

摘要： A process for forming a semiconductor device having an elevated active region is disclosed. The process includes forming a plurality of gate electrodes on the semiconductor substrate and disposing a thick oxide layer over the gate electrodes. A trench is formed in a thick oxide layer and is filled with a polysilicon material. The polysilicon material is subsequently doped in order to form an elevated active region above an active region of the substrate.

摘要翻译： 公开了一种用于形成具有升高的有源区的半导体器件的工艺。 该工艺包括在半导体衬底上形成多个栅电极，并在栅电极上设置厚氧化层。 在厚的氧化物层中形成沟槽并填充有多晶硅材料。 随后掺杂多晶硅材料以便在衬底的有源区上方形成升高的有源区。

公开(公告)号：US6097096A

公开(公告)日：2000-08-01

申请号：US890377

申请日：1997-07-11

申请人： Mark I. Gardner ,  Fred Hause ,  Daniel Kadosh

发明人： Mark I. Gardner ,  Fred Hause ,  Daniel Kadosh

IPC分类号： H01L21/768 ,  H01L21/98 ,  H01L23/532 ,  H01L25/065 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L25/50 ,  H01L21/76801 ,  H01L21/76834 ,  H01L23/5329 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/05571 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/3011

摘要： A high density integrated circuit structure and method of making the same includes providing a first silicon substrate structure having semiconductor device formations in accordance with a first circuit implementation and metal interlevel lines disposed on a top surface thereof and a second silicon substrate structure having a second circuit implementation and metal interlevel lines disposed on a top surface thereof. The first substrate structure includes a planarized low-K dielectric disposed between the metal interlevel lines and a protective coating separating the metal interlevel lines from the low-K dielectric, the metal interlevel lines of the first silicon substrate structure have a melting temperature on the order of less than 500.degree. C. and the low-K dielectric having a dielectric K-value in the range of 2.0-3.8. The second substrate structure also includes a planarized low-K dielectric disposed between the metal interlevel lines and a protective coating separating the metal interlevel lines from the low-K dielectric, the metal interlevel lines having a melting temperature on the order of less than 500.degree. C. and the low-K dielectric having a dielectric K-value in the range of 2.0-3.8. Lastly, the first substrate structure is low temperature bonded to the second substrate structure at respective metal interlevel lines of the first and second substrate structures.

摘要翻译： 高密度集成电路结构及其制造方法包括提供具有根据第一电路实现的半导体器件结构的第一硅衬底结构和设置在其顶表面上的金属层间线以及具有第二电路的第二硅衬底结构 实施和设置在其顶表面上的金属层间线。 第一衬底结构包括设置在金属层间线之间的平面化低K电介质和将金属层间线与低K电介质分开的保护涂层，第一硅衬底结构的金属层间线具有按顺序的熔融温度 小于500℃的低K电介质，介电K值在2.0-3.8范围内。 第二基板结构还包括布置在金属层间线之间的平坦化的低K电介质和将金属层间线与低K电介质隔开的保护涂层，金属层间线具有小于500°的熔融温度 并且介电K值在2.0-3.8范围内的低K电介质。 最后，第一衬底结构在第一和第二衬底结构的相应的金属层间线处被低温地结合到第二衬底结构。

公开(公告)号：US6075268A

公开(公告)日：2000-06-13

申请号：US188972

申请日：1998-11-10

申请人： Mark I. Gardner ,  Daniel Kadosh

发明人： Mark I. Gardner ,  Daniel Kadosh

IPC分类号： H01L21/822 ,  H01L27/06 ,  H01L29/76 ,  H01L23/02 ,  H01L29/94 ,  H01L31/062 ,  H01L31/119

CPC分类号： H01L27/0688 ,  H01L21/8221 ,  H01L2924/0002

摘要： A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds the to the overall circuit density, but does so with emphasis placed on high performance interconnection between devices on separate levels. The interconnect configuration is made as short as possible between features within one transistor level to features within another transistor level. This interconnect scheme lowers resistivity by forming a gate conductor of an upper level transistor upon a gate conductor of lower level transistor. Alternatively, the gate conductors can be a single conductive entity. In order to abut the gate conductors together, or form a single gate conductor, the upper level transistor is inverted relative to the lower level transistor. In addition to the inverted, shared gate conductor, the multi-level transistor fabrication process incorporates formation of openings and filling of those openings to produce interconnect to junctions of the upper/lower transistors. Interconnecting the gate conductors of a pair of stacked transistors and connecting specific junctions of those transistors allows formation of a high density inverter circuit hereof.

摘要翻译： 提供了一种用于在半导体形貌的各种水平上产生有源和无源器件的工艺。 因此，本方法可以实现三维装置的形成，以增强形成集成电路的总体密度。 多级制造工艺不仅增加了整体电路密度，而且重点放在了在不同级别的器件之间的高性能互连。 互连配置在一个晶体管电平内的特征之间尽可能短，在另一个晶体管级内的特征。 该互连方案通过在下级晶体管的栅极导体上形成上层晶体管的栅极导体来降低电阻率。 或者，栅极导体可以是单个导电实体。 为了将栅导体邻接在一起或形成单个栅极导体，上层晶体管相对于下层晶体管反相。 除了反向共享栅极导体之外，多级晶体管制造工艺包括形成开口和填充这些开口以产生与上/下晶体管的结的互连。 将一对堆叠晶体管的栅极导体和这些晶体管的连接特定结之间的互连允许形成其中的高密度反相器电路。

公开(公告)号：US6010957A

公开(公告)日：2000-01-04

申请号：US882423

申请日：1997-06-25

申请人： Mark I. Gardner ,  Daniel Kadosh

发明人： Mark I. Gardner ,  Daniel Kadosh

IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L21/283

CPC分类号： H01L21/76838 ,  H01L23/5283 ,  H01L2924/0002

摘要： A semiconductor device and fabrication process in which tapered conductive lines are formed. Consistent with one embodiment of the invention, a semiconductor device is formed by forming at least one conductive structure over a substrate and forming an insulating layer over the conductive structure. The insulating layer is provided with one or more tapered grooves separated from the conductive structure by a portion of the insulating layer. In each tapered groove a conductive line is formed. The conductive lines may, for example, be metal lines. The conductive structures may, for example, be active regions of a transistor or a previously formed conductive line. A portion of the insulating layer between the conductive layers may be a low dielectric material.

摘要翻译： 形成锥形导电线的半导体器件和制造工艺。 根据本发明的一个实施例，通过在衬底上形成至少一个导电结构并在导电结构上形成绝缘层来形成半导体器件。 绝缘层设置有通过绝缘层的一部分与导电结构分离的一个或多个锥形槽。 在每个锥形槽中形成导线。 导线例如可以是金属线。 导电结构可以例如是晶体管的有源区或者预先形成的导电线。 导电层之间的绝缘层的一部分可以是低电介质材料。

公开(公告)号：US6004849A

公开(公告)日：1999-12-21

申请号：US911745

申请日：1997-08-15

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Michael Duane

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Michael Duane

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/66659 ,  H01L21/28114 ,  H01L29/665 ,  H01L29/7835

摘要： A method of making an asymmetrical IGFET is disclosed. The method includes providing a semiconductor substrate with an active region, wherein the active region includes a source region and a drain region, forming a gate insulator on the active region, forming a gate on the gate insulator and over the active region, implanting arsenic into the active region to provide a greater concentration of arsenic in the source region than in the drain region, growing an oxide layer over the active region, wherein the oxide layer has a greater thickness over the source region than over the drain region due to the greater concentration of arsenic in the source region than in the drain region, forming a source in the source region and a drain in the drain region, depositing a refractory metal over the gate, the source, the drain, and the oxide layer, and reacting the refractory metal with the drain without reacting the refractory metal with the source, thereby forming a silicide contact on the drain without forming a silicide contact on the source. Advantageously, the IGFET has low source-drain resistance, shallow channel junctions, and an LDD that reduces hot carrier effects.

摘要翻译： 公开了制造不对称IGFET的方法。 该方法包括提供具有有源区的半导体衬底，其中有源区包括源极区和漏极区，在有源区上形成栅极绝缘体，在栅极绝缘体上并在有源区上方形成栅极，将砷注入 所述有源区域在所述源极区域中提供比在所述源极区域中更大的砷浓度，在所述有源区域上生长氧化物层，其中所述氧化物层在所述源极区域上比在所述漏极区域上的厚度大于所述漏极区域上的厚度 在源极区域中的砷浓度比漏极区域中的砷浓度高，在源极区域形成源极，在漏极区域形成漏极，在栅极，源极，漏极和氧化物层上沉积难熔金属，并使 具有漏极的难熔金属，而不使难熔金属与源极反应，从而在漏极上形成硅化物接触，而不在源上形成硅化物接触。 有利地，IGFET具有低源极 - 漏极电阻，浅沟道结和降低热载流子效应的LDD。

公开(公告)号：US5882959A

公开(公告)日：1999-03-16

申请号：US729810

申请日：1996-10-08

申请人： Daniel Kadosh ,  Mark I. Gardner

发明人： Daniel Kadosh ,  Mark I. Gardner

IPC分类号： H01L21/822 ,  H01L27/06 ,  H01L21/00

CPC分类号： H01L21/8221 ,  H01L27/0688 ,  Y10S257/905

摘要： A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect achieves lower resistivity and capacitance by forming a single gate conductor which is shared by an upper level transistor and a lower level transistor. The shared gate conductor is interposed between a pair of gate dielectrics and each gate dielectric is configured between the single gate conductor and a respective substrate. Thus, the upper level transistor is inverted relative to the lower level transistor. The upper level transistor includes a substrate and junction region formed within and opening of an interlevel dielectric. The opening serves to receive the substrate material, but also to demarcate the formation of a pre-existing gate dielectric prior to substrate deposition. Sharing a single gate conductor among two transistors not only minimizes the overall routing between transistor inputs, but also is particularly attuned to inverter formation.

公开(公告)号：US5866934A

公开(公告)日：1999-02-02

申请号：US879504

申请日：1997-06-20

申请人： Daniel Kadosh ,  Mark I. Gardner ,  Jon D. Cheek

发明人： Daniel Kadosh ,  Mark I. Gardner ,  Jon D. Cheek

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H01L29/423 ,  H01L27/11

CPC分类号： H01L29/66659 ,  H01L21/28114 ,  H01L21/2815 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/41775 ,  H01L29/42376 ,  Y10S257/904 ,  Y10S438/947

摘要： An improved series and/or parallel connection of transistors within a logic gate is presented. The improved connection is brought about by a sacrificial structure on which gate conductors are formed adjacent sidewall surfaces of the sacrificial structure. The sacrificial structure thereby provides spacing between the series-connected or parallel-connected transistors. Upon removal of each sacrificial structure, a pair of transistors can be formed by implanting dopant species into the substrate on opposite sides of the spaced conductors. Beneath what was once a sacrificial structure is a shared implant area to which two transistors are coupled either in series or in parallel. By depositing the gate conductor material and then anisotropically removing the material except adjacent the vertical sidewall surfaces, an ultra short gate conductor can be formed concurrent with other gate conductors within a logic gate.

公开(公告)号：US5854115A

公开(公告)日：1998-12-29

申请号：US979042

申请日：1997-11-26

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Michael P. Duane

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Michael P. Duane

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/51

CPC分类号： H01L29/518 ,  H01L21/28052 ,  H01L21/28176 ,  H01L21/823456 ,  H01L21/823828 ,  H01L21/82385 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66598 ,  Y10S438/97

摘要： A process is provided for forming a transistor gate conductor having an etch stop arranged at a depth below its upper surface such that the lateral width of the gate conductor above the etch stop may be exclusively narrowed to provide for reduction of transistor channel length. A masking layer, i.e., photoresist, patterned above the gate conductor is isotropically etched so as to minimize its lateral width prior to etching the gate conductor. Portions of the gate conductor not protected by the photoresist may be etched from above the etch stop to define a new pair of opposed sidewall surfaces for the upper portion of the gate conductor. The lateral width of the upper portion of the gate conductor thus may be reduced to a smaller dimension than that of conventional gate conductors. The gate conductor is subjected to an anisotropic etch in which portions of the gate conductor not protected by the narrowed photoresist are etched down to the etch stop. The presence of the etch stop ensures that substantial portions of the etch stop and underlying portions of the gate conductor are not removed before etching is completely terminated. As a result, a lower portion of the multi-layered gate conductor is wider than an upper portion of the gate conductor.

摘要翻译： 提供了一种用于形成晶体管栅极导体的工艺，该晶体管栅极导体具有布置在其上表面下方的深度处的蚀刻停止，使得蚀刻停止点之上的栅极导体的横向宽度可以专门变窄以提供晶体管沟道长度的减小。 在栅极导体上形成图案的掩模层，即光致抗蚀剂被各向同性蚀刻，以便在蚀刻栅极导体之前将其横向宽度最小化。 未被光致抗蚀剂保护的栅极导体的部分可以从蚀刻停止点的上方蚀刻，以限定用于栅极导体的上部的新的一对相对的侧壁表面。 因此，栅极导体的上部的横向宽度可以减小到比常规栅极导体更小的尺寸。 对栅极导体进行各向异性蚀刻，其中不被变窄的光致抗蚀剂保护的栅极导体的部分被蚀刻到蚀刻停止点。 蚀刻停止的存在确保蚀刻停止的大部分和栅极导体的下面的部分在蚀刻完全终止之前不被去除。 结果，多层栅极导体的下部比栅极导体的上部宽。

公开(公告)号：US5851883A

公开(公告)日：1998-12-22

申请号：US844975

申请日：1997-04-23

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Fred N. Hause

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Fred N. Hause

IPC分类号： H01L21/8234

CPC分类号： H01L21/823437 ,  Y10S438/947

摘要： A semiconductor process in which a dielectric layer is formed on an upper surface of a semiconductor substrate which includes a silicon base layer. Thereafter, an upper silicon layer is formed on an upper surface of the dielectric layer. The dielectric layer and the upper silicon layer are then patterned to form first and second silicon-dielectric stacks on the upper surface of the base silicon layer. The first and second silicon-dielectric stacks are laterally displaced on either side of a channel region of the silicon substrate and each include a proximal sidewall and a distal sidewall. The proximal sidewalls are approximately coincident with respective boundaries of the channel region. Thereafter, proximal and distal spacer structures are formed on the proximal and distal sidewalls respectively of the first and second silicon-dielectric stacks. A gate dielectric layer is then formed on exposed portions of the silicon base layer over a channel region of the base silicon layer. Portions of the first and second silicon-dielectric stacks located over respective source/drain regions of the base silicon layer are then selectively removed. Silicon is then deposited to fill first and second voids created by the selected removal of the stacks. The silicon deposition also fills a silicon gate region above the gate dielectric over the channel region. Thereafter, an impurity distribution is introduced into the deposited silicon. The deposited silicon is then planarized to physically isolate the silicon within the gate region from the silicon within the first and second voids resulting in the formation of a transistor including a silicon gate structure and first and second source/drain structures.

摘要翻译： 在包括硅基层的半导体衬底的上表面上形成介电层的半导体工艺。 此后，在电介质层的上表面上形成上硅层。 然后对电介质层和上硅层进行构图以在基底硅层的上表面上形成第一和第二硅 - 电介质叠层。 第一和第二硅 - 电介质堆叠在硅衬底的沟道区域的任一侧上横向移位，并且每个包括近侧壁和远侧壁。 近侧侧壁与通道区域的各个边界大致重合。 此后，分别在第一和第二硅 - 电介质堆叠的近侧和远侧壁上形成近端和远端间隔结构。 然后在硅基层的暴露部分上在基底硅层的沟道区上形成栅极电介质层。 然后选择性地去除位于基底硅层的相应源极/漏极区域之上的第一和第二硅 - 电介质叠层的部分。 然后沉积硅以填充由所选择的堆叠移除产生的第一和第二空隙。 硅沉积还在沟道区域上填充栅极电介质上方的硅栅极区域。 此后，将杂质分布引入沉积的硅中。 沉积的硅然后被平坦化以物理地隔离第一和第二空隙内的栅极区域内的硅，从而形成包括硅栅极结构和第一和第二源极/漏极结构的晶体管。