公开(公告)号：US20080071963A1

公开(公告)日：2008-03-20

申请号：US11979103

申请日：2007-10-31

申请人： David Chow ,  Sidney Young ,  Charles Lee ,  Abraham Ma ,  Ming-Shiang Shen

发明人： David Chow ,  Sidney Young ,  Charles Lee ,  Abraham Ma ,  Ming-Shiang Shen

IPC分类号： G06F13/20 ,  G06F12/02

CPC分类号： G06F13/409 ,  G06F2213/0026 ,  G06F2213/0042 ,  Y02D10/14 ,  Y02D10/151

摘要： An ExpressCard having USB connection has a card case having two opposite first and second end portions and two opposite lateral portions. A card connector is formed at the first end portion of the card case and having a USB interface. Flash chips are implemented in the card case. A USB flash controller implemented in the card case and connected between the USB interface and the flash chips in order to provide a data access to the flash chips through the USB interface. A USB socket, in form factors of Mini-USB or Extended Mini-connector-type, is implemented in the card case and connected to the USB flash controller in order to provide a data access to the one or more flash chips therethrough. An extended Universal-Serial Bus (EUSB) host enters a suspend mode rather than poll an ExpressCard that is busy performing a memory or other operation, thereby saving power.

摘要翻译： 具有USB连接的ExpressCard具有具有两个相对的第一和第二端部和两个相对的横向部分的卡盒。 卡连接器形成在卡盒的第一端部并且具有USB接口。 闪存芯片在卡盒中实现。 USB闪存控制器实现在卡盒中并连接在USB接口和闪存芯片之间，以通过USB接口提供对闪存芯片的数据访问。 一个USB插座，以Mini-USB或扩展迷你连接器类型的形式被实现在卡盒中并连接到USB闪存控制器，以便提供对一个或多个闪存芯片的数据访问。 扩展的通用串行总线（EUSB）主机进入挂起模式，而不是轮询正忙于执行内存或其他操作的ExpressCard，从而节省电量。

公开(公告)号：US20080086631A1

公开(公告)日：2008-04-10

申请号：US11864652

申请日：2007-09-28

申请人： David Chow ,  Charles Lee ,  Frank Yu ,  Edward Lee ,  Ming-Shiang Shen

发明人： David Chow ,  Charles Lee ,  Frank Yu ,  Edward Lee ,  Ming-Shiang Shen

IPC分类号： G06F15/177 ,  G06F12/02

CPC分类号： G06F8/654

摘要： An electronic data flash card is accessible by a host system, and includes a flash memory controller and at least one flash memory device coupled to the flash controller. The boot code and control code for the flash memory system (flash card) are stored in the flash memory device during a programming procedure. The flash controller transfers the boot code and control code to a volatile main memory (e.g., random access memory or RAM) at start up or reset making a RAM-based memory system. Boot code and control code are selectively overwritten during a code updating operation. A single flash controller thus supports multiple brands and types of flash memory to eliminate stocking issues.

摘要翻译： 电子数据闪存卡可由主机系统访问，并且包括闪存控制器和耦合到闪存控制器的至少一个闪存设备。 闪存系统（闪存卡）的启动代码和控制代码在编程过程中存储在闪存设备中。 闪存控制器在启动或复位时将引导代码和控制代码传送到易失性主存储器（例如，随机存取存储器或RAM），从而形成基于RAM的存储器系统。 引导代码和控制代码在代码更新操作期间被有选择地覆盖。 因此，单个闪存控制器支持多种品牌和类型的闪存，以消除存货问题。

公开(公告)号：US20080052507A1

公开(公告)日：2008-02-28

申请号：US11838192

申请日：2007-08-13

申请人： David Chow ,  Charles Lee ,  Frank Yu ,  Tzu-Yih Chu ,  Ming-Shiang Shen

发明人： David Chow ,  Charles Lee ,  Frank Yu ,  Tzu-Yih Chu ,  Ming-Shiang Shen

IPC分类号： G06F13/38 ,  G06F1/24 ,  G06F21/00 ,  G06F9/06

CPC分类号： G06F21/568 ,  G06F21/575 ,  G06F2221/2105 ,  G06F2221/2153

摘要： A multi-partition Universal Serial Bus (USB) device has a flash memory with multiple partitions of storage. Some partitions are for different operating systems and store OS images. Another partition has a control program while a user partition stores user data and user configuration information. The control program can test the multi-partition USB device and instruct the host computer BIOS to mount a partition from its flash memory as a drive of the host computer. The host computer can then be rebooted. The OS image from the flash memory is loaded into main memory during rebooting, and the host computer executes a new operating system using the new OS image. The user can press buttons on the multi-partition USB device to select which OS to load, and to begin rebooting. Virus removal programs in the alternate OS can help recover from a virus in the primary OS.

摘要翻译： 多分区通用串行总线（USB）设备具有具有多个存储分区的闪存。 一些分区用于不同的操作系统并存储操作系统映像。 另一个分区具有控制程序，而用户分区则存储用户数据和用户配置信息。 控制程序可以测试多分区USB设备，并指示主机BIOS将其闪存中的分区作为主机的驱动器安装。 然后可以重新启动主机。 重新启动时，闪存中的OS映像将加载到主内存中，主机使用新的操作系统映像执行新的操作系统。 用户可以按多分区USB设备上的按钮选择要加载的操作系统，并开始重新启动。 备用操作系统中的病毒清除程序可以帮助从主操作系统中的病毒恢复。

公开(公告)号：US20080082813A1

公开(公告)日：2008-04-03

申请号：US11861133

申请日：2007-09-25

申请人： David Chow ,  Edward Lee ,  Abraham Ma ,  Ming-Shiang Shen

发明人： David Chow ,  Edward Lee ,  Abraham Ma ,  Ming-Shiang Shen

IPC分类号： G06F15/177 ,  H04L9/00 ,  H04L9/30

CPC分类号： G06F21/34 ,  G06F21/575 ,  H04L9/0897 ,  H04L9/3234 ,  H04L63/08 ,  H04L2209/603

摘要： Techniques for booting a host computer from a portable storage device with customized settings with secure measure are described herein. According to one embodiment, in response to detecting a portable storage device inserted into a first host computer, the portable storage device is authenticated using a private key stored within the portable storage device against a public key stored in a second host computer over a network. In response to a successful authentication, data representing a personal working environment associated with a user of the portable storage device is downloaded from the second host computer over the network. After reboot, the first host computer is configured using the obtained settings of the personal working environment, such that the user of the portable storage device can operate the second host computer in view of the personal working environment. Other methods and apparatuses are also described.

摘要翻译： 本文描述了用于通过具有安全措施的定制设置从便携式存储设备引导主计算机的技术。 根据一个实施例，响应于检测到插入到第一主计算机中的便携式存储装置，使用存储在便携式存储装置内的专用密钥，通过网络对存储在第二主计算机中的公开密钥来认证便携式存储装置。 响应于成功的认证，表示与便携式存储设备的用户相关联的个人工作环境的数据通过网络从第二主计算机被下载。 在重新启动之后，使用所获得的个人工作环境的设置来配置第一主计算机，使得便携式存储设备的用户可以根据个人工作环境操作第二主计算机。 还描述了其它方法和装置。

公开(公告)号：US20080016269A1

公开(公告)日：2008-01-17

申请号：US11773827

申请日：2007-07-05

申请人： David Chow ,  Charles Lee ,  Frank Yu

发明人： David Chow ,  Charles Lee ,  Frank Yu

IPC分类号： G06F12/00

CPC分类号： G06F13/1684 ,  G11C13/0004 ,  G11C16/102 ,  G11C2216/30

摘要： A multi-ring memory controller sends request packets to multiple rings of serial flash-memory chips. Each of the multiple rings has serial flash-memory chips with serial links in a uni-directional ring. Each serial flash-memory chip has a bypassing transceiver with a device ID checker that bypasses serial packets to a clock re-synchronizer and bypass logic for retransmission to the next device in the ring, or extracts the serial packet to the local device when an ID match occurs. Serial packets pass through all devices in the ring during one round-trip transaction from the controller. The average latency of one round is constant for all devices on the ring, reducing data-dependent performance, since the same packet latency occurs regardless of the data location on the ring. The serial links can be a Peripheral Component Interconnect (PCI) Express bus. Packets have modified-PCI-Express headers that define the packet type and data-payload length.

摘要翻译： 多环存储器控制器将请求数据包发送到串行闪存芯片的多个环。 多个环中的每个环都具有串行闪存芯片，其具有单向环中的串行链路。 每个串行闪存芯片都具有一个旁路收发器，其中设备ID检查器将串行数据包绕过时钟重新同步器，并且旁路逻辑用于重传到环中的下一个设备，或者当ID为ID时将串行数据包提取给本地设备 匹配发生。 在来自控制器的一次往返事务期间，串行数据包通过环中的所有设备。 由于相同的数据包延迟发生，环路上的所有设备的平均延迟都是恒定的，从而降低了数据相关性能，无论环的数据位置如何。 串行链路可以是外围组件互连（PCI）Express总线。 数据包已经修改了PCI-Express头，定义了数据包类型和数据有效负载长度。

公开(公告)号：US20070204128A1

公开(公告)日：2007-08-30

申请号：US11742270

申请日：2007-04-30

申请人： Charles Lee ,  Frank Yu ,  David Chow

发明人： Charles Lee ,  Frank Yu ,  David Chow

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7211

摘要： A restrictive multi-level-cell (MLC) flash memory prohibits regressive page-writes. When a regressive page-write is requested, an empty block having a low wear-level count is found, and data from the regressive page-write and data from pages stored in the old block are written to the empty block in page order. The old block is erased and recycled. A two-level look-up table is stored in volatile random-access memory (RAM). A logical page address from a host is divided by a modulo divider to generate a quotient and a remainder. The quotient is a logical block address that indexes a first-level look-up table to find a mapping entry with a physical block address that selects a row in a second-level look-up table. The remainder locates a column in the row in the second-level look-up table. If any page-valid bits above the column pointed to by the remainder are set, the write is regressive.

摘要翻译： 限制性多电平单元（MLC）闪存禁止回归页面写入。 当请求回归页面写入时，找到具有低磨损级别计数的空块，并且按页顺序将存储在旧块中的页面写入的数据和来自页面的页面的数据写入空块。 旧区被擦除并回收。 两级查找表存储在易失性随机存取存储器（RAM）中。 来自主机的逻辑页地址由模分隔器除以生成商和余数。 商是一个逻辑块地址，其索引第一级查找表以找到具有在二级查找表中选择行的物理块地址的映射条目。 剩余部分在二级查找表中的行中找到一列。 如果设置了剩余部分指向的列之上的任何页面有效位，则写入是回归的。

公开(公告)号：US20070255891A1

公开(公告)日：2007-11-01

申请号：US11770642

申请日：2007-06-28

申请人： David Chow ,  Charles Lee ,  Frank Yu

发明人： David Chow ,  Charles Lee ,  Frank Yu

IPC分类号： G06F12/00

CPC分类号： G06F12/0804 ,  G06F12/0238 ,  G06F13/16 ,  G06F13/161 ,  G06F2212/1016 ,  G06F2212/2022 ,  G11C7/10 ,  G11C7/1015 ,  G11C8/08 ,  G11C8/12 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2211/5641 ,  G11C2213/79

摘要： Peripheral devices store data in non-volatile phase-change memory (PCM). PCM cells have alloy resistors with high-resistance amorphous states and low-resistance crystalline states. The peripheral device can be a Multi-Media Card/Secure Digital (MMC/SD) card. A PCM controller accesses PCM memory devices. Various routines that execute on a CPU in the PCM controller are activated in response to commands in the host-bus transactions. The PCM system increases the throughput of one or more phase-change memory devices by performing one or more of a read-ahead memory operation, a write-ahead memory write operation, a larger page memory write operation, a wider data bus memory write operation, a multi-channel concurrent multi-bank interleaving memory read or write operation, a write-cache memory write operation, and any combination thereof.

摘要翻译： 外围设备将数据存储在非易失性相变存储器（PCM）中。 PCM单元具有具有高电阻非晶态和低电阻晶体态的合金电阻。 外围设备可以是多媒体卡/安全数字（MMC / SD）卡。 PCM控制器访问PCM存储器设备。 响应于主机总线事务中的命令，激活在PCM控制器中的CPU上执行的各种例程。 PCM系统通过执行预读存储器操作，预写存储器写操作，较大页存储器写操作，更宽数据总线存储器写操作中的一个或多个来增加一个或多个相变存储器件的吞吐量 多通道同时多存储体交错存储器读或写操作，写高速缓存存储器写操作及其任意组合。

公开(公告)号：US20070276988A1

公开(公告)日：2007-11-29

申请号：US11779804

申请日：2007-07-18

申请人： Jianjun Luo ,  Chris Tsu ,  Charles Lee ,  David Chow

发明人： Jianjun Luo ,  Chris Tsu ,  Charles Lee ,  David Chow

IPC分类号： G06F13/28

CPC分类号： G06F12/0246 ,  G06F12/0292 ,  G06F13/28 ,  G06F2212/1036 ,  G06F2212/7211

摘要： A flash controller is adapted to communicate with a host and the flash memory and including volatile memory configured to store a page-block table of logical addresses addressable by the physical addresses. The logical addresses are used by the controller to identify the blocks. The table has an address mapping table and a property value table, the property value table includes property values, each of the property values being increased in value every time a block is written up to a maximum value and being associated with a block of a predetermined group of blocks and indicative of the number of times a block has been written, the property values corresponding to the logical addresses of the address mapping table, wherein the maximum number the property values of the predetermined group of blocks take on is adjustably different than the maximum number the property values of another group of blocks.

摘要翻译： 闪存控制器适于与主机和闪存进行通信，并且包括被配置为存储可通过物理地址寻址的逻辑地址的页块表的易失性存储器。 逻辑地址由控制器用于识别块。 该表具有地址映射表和属性值表，属性值表包括属性值，每当一个块写入最大值并且与预定的块相关联时，每个属性值都被增加， 指示块的写入次数的一组块，对应于地址映射表的逻辑地址的属性值，其中预定块组的属性值的最大数量可以与 最大数量的另一组块的属性值。

公开(公告)号：US20080037321A1

公开(公告)日：2008-02-14

申请号：US11774906

申请日：2007-07-09

申请人： Jianjun Luo ,  Chris Tsu ,  Charles Lee ,  David Chow

发明人： Jianjun Luo ,  Chris Tsu ,  Charles Lee ,  David Chow

IPC分类号： G11C16/06

CPC分类号： G11C16/102 ,  G06F8/65 ,  G11C2211/5641

摘要： A flash memory system includes a multi level cell (MLC) flash memory organized into blocks and having pages of information, which has data and spare. The MLC flash memory includes at least a temporary area to store at least a portion of a page of information during a partial write operation. The MLC flash memory stores a page of information into a block identified by a target physical address. The flash memory system further includes a flash card micro-controller causes communication between a host flash card controller and the MLC flash memory and includes a buffer memory configured to store a portion of a page of information, where the micro-controller writes the at least a portion of a page of information to the temporary area and later copies the written at least a portion of a page of information into the block identified by a target physical address.

摘要翻译： 闪存系统包括组织成块并具有数据和备用的信息页的多级单元（MLC）闪存。 在部分写入操作期间，MLC闪速存储器至少包括用于存储信息页的至少一部分的临时区域。 MLC闪速存储器将一页信息存储到由目标物理地址识别的块中。 闪存系统还包括闪存卡微控制器引起主机闪存卡控制器和MLC闪速存储器之间的通信，并且包括被配置为存储信息页的一部分的缓冲存储器，其中微控制器写入至少 信息页面的一部分到临时区域，并且稍后将写入信息页的至少一部分复制到由目标物理地址识别的块中。

公开(公告)号：US20070276987A1

公开(公告)日：2007-11-29

申请号：US11767417

申请日：2007-06-22

申请人： Jianjun Luo ,  Chris Tsu ,  Charles Lee ,  David Chow

发明人： Jianjun Luo ,  Chris Tsu ,  Charles Lee ,  David Chow

IPC分类号： G06F12/02

CPC分类号： G06F13/28 ,  G06F12/0246 ,  G06F12/0292 ,  G06F2212/1036 ,  G06F2212/7211

摘要： A flash memory system includes flash memory organized into a plurality of blocks of pages for storage of information, a page including data and spare, the blocks being identifiable, within the flash memory, by a physical address. The system further has a flash controller for communicating with a host and the flash memory and includes volatile memory for storing a source-shadow table of logical addresses identifying blocks addressable by the physical addresses. The source-shadow table has an address mapping table and a property value table. The property value table is used to store property values, each of which is associated with a block of a predetermined group of blocks and is indicative of the number of times a block has been written since the last erase operation performed thereon. The property values correspond to the logical addresses of the address mapping table, wherein a block having been written no more than two times is re-written to different areas of the flash memory without requiring an erase operation.

摘要翻译： 闪速存储器系统包括组织成多个页面块的闪存，用于存储信息，包括数据和备用的页面，所述块可被闪存存储器内的物理地址识别。 该系统还具有用于与主机和闪速存储器进行通信的闪存控制器，并且包括用于存储识别通过物理地址可寻址的块的逻辑地址的源影子表的易失性存储器。 source-shadow表有一个地址映射表和一个属性值表。 属性值表用于存储属性值，每个属性值与预定块块组相关联，并且表示自上次执行的上次擦除操作以来写入块的次数。 属性值对应于地址映射表的逻辑地址，其中已经写入不超过两次的块被重写到闪速存储器的不同区域，而不需要擦除操作。