公开(公告)号：US07324548B2

公开(公告)日：2008-01-29

申请号：US10355472

申请日：2003-01-31

Applicant: Vikram Natarajan ,  Kang Xiao ,  Mario Caresosa ,  Jay Proano ,  David Chung ,  Afshin Momtaz ,  Randy Stolaruk ,  Xin Wang ,  Namik Kocaman

Inventor： Vikram Natarajan ,  Kang Xiao ,  Mario Caresosa ,  Jay Proano ,  David Chung ,  Afshin Momtaz ,  Randy Stolaruk ,  Xin Wang ,  Namik Kocaman

IPC: H04J3/16 ,  H04J3/22 ,  H04J14/00 ,  H04B10/00

CPC classification number: H04Q11/0478 ,  H04J3/04 ,  H04J3/0685 ,  H04J3/1611 ,  H04J2203/0046 ,  H04J2203/0067 ,  H04J2203/0082 ,  H04J2203/0089 ,  Y10S370/907

Abstract: Present herein is a multirate transceiver wherein data can be received at a first data rate and transmitted at a second data rate. The transceiver device comprises a first interface for receiving data at one data rate a mapper that can map data from a first rate to the second rate, and a second interface for transmitting the data at the second data rate.

Abstract translation: 本发明是一种多速率收发器，其中可以以第一数据速率接收数据并以第二数据速率发送数据。 收发器装置包括用于以一个数据速率接收能够将数据从第一速率映射到第二速率的映射器的数据的第一接口和用于以第二数据速率发送数据的第二接口。

公开(公告)号：US20050271169A1

公开(公告)日：2005-12-08

申请号：US10880959

申请日：2004-06-30

Applicant: Afshin Momtaz ,  Mario Caresosa ,  David Chung ,  Davide Tonietto ,  Guangming Yin ,  Bruce Currivan ,  Thomas Kolze ,  Ichiro Fujimori

Inventor： Afshin Momtaz ,  Mario Caresosa ,  David Chung ,  Davide Tonietto ,  Guangming Yin ,  Bruce Currivan ,  Thomas Kolze ,  Ichiro Fujimori

IPC: H03G3/30 ,  H03L7/091 ,  H04L7/02 ,  H04L7/033 ,  H04L25/03 ,  H04L27/08

CPC classification number: H04L7/033 ,  H03G3/3084 ,  H03L7/091 ,  H04L25/03057 ,  H04L2025/03375 ,  H04L2025/03617

Abstract: Equalization is provided in a high speed communication receiver that includes in various aspects an automatic gain control input stage, a decision feedback equalizer, a clock and data recovery circuit and equalization control circuits. The automatic gain control stage may include a continuous time filter with an adjustable bandwidth. A threshold adjust signal may be applied to the output of the automatic gain control stage. The equalization control circuits may be implemented in the digital domain and operate at a lower clock speed than the data path.

Abstract translation: 在高速通信接收机中提供均衡，其包括各种方面的自动增益控制输入级，判决反馈均衡器，时钟和数据恢复电路以及均衡控制电路。 自动增益控制级可以包括具有可调节带宽的连续时间滤波器。 阈值调整信号可以应用于自动增益控制级的输出。 均衡控制电路可以在数字域中实现并且以比数据路径更低的时钟速度工作。

公开(公告)号：US06696854B2

公开(公告)日：2004-02-24

申请号：US09956374

申请日：2001-09-17

Applicant: Afshin Momtaz ,  Xin Wang ,  Jun Cao ,  Armond Hairapetian ,  David Chung

Inventor： Afshin Momtaz ,  Xin Wang ,  Jun Cao ,  Armond Hairapetian ,  David Chung

IPC: G11C700

CPC classification number: G06F5/10 ,  G06F2205/106

Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

公开(公告)号：US20050248382A1

公开(公告)日：2005-11-10

申请号：US10840524

申请日：2004-05-06

Applicant: David Chung ,  Afshin Momtaz ,  Mario Caresosa

Inventor： David Chung ,  Afshin Momtaz ,  Mario Caresosa

IPC: G06G7/12

CPC classification number: H03F3/4508 ,  H03F2200/456 ,  H03F2200/465 ,  H03F2203/45292 ,  H03F2203/45541

Abstract: A compensation apparatus maintains an effective resistance of one or more resistors in a circuit by associating an adjustable resistor circuit to each resistor. The compensation apparatus compares the resistance of a resistor in the circuit with the resistance of a reference resistor. When the resistance of the resistor in the circuit falls outside of a desired range, the compensation apparatus adjusts the resistance of the adjustable resistor to adjust the effective resistance of the resistor and adjustable resistor combination.

Abstract translation: 补偿装置通过将可调电阻器电路与每个电阻器相关联来保持电路中的一个或多个电阻器的有效电阻。 补偿装置将电路中的电阻器的电阻与参考电阻器的电阻进行比较。 当电路中的电阻电阻超出所需范围时，补偿装置调整可调电阻的电阻，调整电阻和可调电阻组合的有效电阻。

公开(公告)号：US06963220B2

公开(公告)日：2005-11-08

申请号：US10749965

申请日：2003-12-31

Applicant: Afshin Momtaz ,  Xin Wang ,  Jun Cao ,  Armond Hairapetian ,  David Chung

Inventor： Afshin Momtaz ,  Xin Wang ,  Jun Cao ,  Armond Hairapetian ,  David Chung

IPC: G06F5/10 ,  G11C7/00

CPC classification number: G06F5/10 ,  G06F2205/106

Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

Abstract translation: 用于实现高速先进先出（FIFO）结构的方法和电路。 在一个实施例中，公开了允许一个时钟（例如写时钟）的频率与另一（读取）时钟的频率不同的（例如，一半）的FIFO。 在另一个实施例中，呈现可以异步地设置和/或复位的FIFO。 公开了其他实施例，其中有效地监视读取和写入指针，以确保正确的时序关系，以检测时钟损耗以及检测其他异常FIFO条件。

公开(公告)号：US06940306B2

公开(公告)日：2005-09-06

申请号：US10750098

申请日：2003-12-31

Applicant: Afshin Momtaz ,  Xin Wang ,  Jun Cao ,  Armond Hairapetian ,  David Chung

Inventor： Afshin Momtaz ,  Xin Wang ,  Jun Cao ,  Armond Hairapetian ,  David Chung

IPC: G06F5/10 ,  G11C7/00

CPC classification number: G06F5/10 ,  G06F2205/106

Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

公开(公告)号：US20120328063A1

公开(公告)日：2012-12-27

申请号：US13168861

申请日：2011-06-24

Applicant: Anand Jitendra Vasani ,  Jun Cao ,  Afshin Momtaz

Inventor： Anand Jitendra Vasani ,  Jun Cao ,  Afshin Momtaz

IPC: H04L7/02

CPC classification number: H04L7/0079 ,  H03L7/0812 ,  H04L7/033

Abstract: Provided is a low latency high bandwidth clock and data recovery (CDR) system. For example, there is a low latency high bandwidth CDR system including a demultiplexer configured to convert a high frequency input datastream to a low frequency output datastream according to a first latency and a phase error processor at least partially embedded into the demultiplexer and configured to determine a datastream phase error of the high frequency input datastream according to a second latency. The embedded phase error processor allows a portion of a total latency of the CDR system due to the demultiplexer and the phase error processor to be less than a sum of the first and second latencies.

Abstract translation: 提供了低延迟高带宽时钟和数据恢复（CDR）系统。 例如，存在低延迟高带宽CDR系统，其包括解复用器，其被配置为根据第一等待时间将高频输入数据流转换为低频输出数据流，并且相位误差处理器至少部分地被嵌入到解复用器中并且被配置为确定 根据第二等待时间，高频输入数据流的数据流相位误差。 嵌入式相位误差处理器允许由于解复用器和相位误差处理器而导致的CDR系统的总等待时间的一部分小于第一和第二延迟的和。

公开(公告)号：US08077060B2

公开(公告)日：2011-12-13

申请号：US12582442

申请日：2009-10-20

Applicant: Afshin Momtaz ,  Namik K. Kocaman ,  Bharath Raghavan

Inventor： Afshin Momtaz ,  Namik K. Kocaman ,  Bharath Raghavan

IPC: H03M7/00

CPC classification number: H03F3/45475 ,  H03F3/45183 ,  H03F2203/45686

Abstract: According to one general aspect, an apparatus may include a terminal configured to receive an analog input signal. In various embodiments, the apparatus may also include a multistage amplifier configured to amplify the analog input signal by an amount of gain. In some embodiments, the apparatus may include a distributed threshold adjuster interspersed between the stages of the multistage amplifier configured to adjust the DC voltage of the analog input signal to facilitate a decision by an analog-to-digital converter (ADC). In one embodiment, the apparatus may include the ADC configured to convert the amplified analog input signal to a digital output signal.

Abstract translation: 根据一个一般方面，装置可以包括被配置为接收模拟输入信号的终端。 在各种实施例中，该装置还可以包括多级放大器，其被配置为将模拟输入信号放大一定量的增益。 在一些实施例中，该装置可以包括散布在多级放大器的级之间的分布式阈值调节器，其被配置为调整模拟输入信号的DC电压以便于模数转换器（ADC）的决定。 在一个实施例中，该装置可以包括被配置为将放大的模拟输入信号转换成数字输出信号的ADC。

公开(公告)号：US07974337B2

公开(公告)日：2011-07-05

申请号：US12606751

申请日：2009-10-27

Applicant: Afshin Momtaz ,  Mario Caresosa ,  David Kyong-Sik Chung ,  Davide Tonietto ,  Guangming Yin ,  Bruce Currivan ,  Thomas Kolze ,  Ichiro Fujimori

Inventor： Afshin Momtaz ,  Mario Caresosa ,  David Kyong-Sik Chung ,  Davide Tonietto ,  Guangming Yin ,  Bruce Currivan ,  Thomas Kolze ,  Ichiro Fujimori

IPC: H03H7/30

CPC classification number: H04L7/033 ,  H03G3/3084 ,  H03L7/091 ,  H04L25/03057 ,  H04L2025/03375 ,  H04L2025/03617

Abstract: Various example embodiments are disclosed. According to an example embodiment, an apparatus may include a continuous time filter, a decision feedback equalizer, a clock and data recovery circuit, and an adaptation circuit. The adaptation circuit may be configured to adapt equalization according to at least one dithering algorithm by adjusting a delay adjust signal based on a mean square error of equalized data signals.

Abstract translation: 公开了各种示例性实施例。 根据示例实施例，设备可以包括连续时间滤波器，判决反馈均衡器，时钟和数据恢复电路以及适配电路。 适配电路可以被配置为通过基于均衡数据信号的均方误差调整延迟调整信号来根据至少一个抖动算法来适应均衡。

公开(公告)号：US07769110B2

公开(公告)日：2010-08-03

申请号：US11128905

申请日：2005-05-13

Applicant: Afshin Momtaz

Inventor： Afshin Momtaz

IPC: H04L25/06

CPC classification number: H04L25/061 ,  H04L7/033 ,  H04L25/03057

Abstract: An adaptive algorithm is implemented that optimizes the slicer threshold by optimizing the tail distribution of a “+1” and “−1” histogram. Through the use of a low resolution and under-sampled ADC, a histogram of received bit may be created. The difference between the y-intersects of lines derived from the “+1” and “−1” histogram is used to determine an error function. The algorithm iteratively updates the threshold value based on this error function.

Abstract translation: 实现了通过优化“+1”和“-1”直方图的尾部分布来优化限幅器阈值的自适应算法。 通过使用低分辨率和欠采样ADC，可以创建接收位的直方图。 使用从“+1”和“-1”直方图导出的线的y相交之间的差异来确定误差函数。 该算法基于该误差函数迭代地更新阈值。