公开(公告)号：US20070298333A1

公开(公告)日：2007-12-27

申请号：US11734818

申请日：2007-04-13

申请人： Daniele Piumi ,  Gianfranco Capetti ,  Simone Alba ,  Carlo Demuro ,  Danilo De Simone

发明人： Daniele Piumi ,  Gianfranco Capetti ,  Simone Alba ,  Carlo Demuro ,  Danilo De Simone

IPC分类号： G03F1/00

CPC分类号： H01L21/0271 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3088

摘要： A process for manufacturing an organic mask for the microelectronics industry, including forming an organic layer on a substrate; forming an inorganic mask on the organic layer; and etching selectively the organic layer through the inorganic mask. Furthermore, forming the inorganic mask includes forming at least a first auxiliary layer of a first inorganic material on the organic layer; forming a mask layer of a second inorganic material different from the first inorganic material on the first auxiliary layer; and shaping the mask layer using a dual-exposure lithographic process.

摘要翻译： 一种用于制造微电子工业的有机掩模的方法，包括在衬底上形成有机层; 在有机层上形成无机掩模; 并通过无机掩模选择性地蚀刻有机层。 此外，形成无机掩模包括在有机层上至少形成第一无机材料的第一辅助层; 在所述第一辅助层上形成与所述第一无机材料不同的第二无机材料的掩模层; 以及使用双曝光光刻工艺成形掩模层。

公开(公告)号：US20060073651A1

公开(公告)日：2006-04-06

申请号：US11294763

申请日：2005-12-06

申请人： Francesco Ciovacco ,  Simone Alba ,  Roberto Colombo ,  Chiara Savardi

发明人： Francesco Ciovacco ,  Simone Alba ,  Roberto Colombo ,  Chiara Savardi

IPC分类号： H01L21/8238 ,  H01L21/302

CPC分类号： H01L21/823437 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76804 ,  H01L21/76816

摘要： A method for manufacturing semiconductor-integrated electronic circuits includes: depositing an auxiliary layer on a substrate; depositing a layer of screening material on the auxiliary layer; selectively removing the layer of screening material to provide a first opening in the layer of screening material and expose an area of the auxiliary layer; and removing this area of the auxiliary layer to form a second opening in the auxiliary layer, whose cross-section narrows toward the substrate to expose an area of the substrate being smaller than the area exposed by the first opening.

摘要翻译： 一种半导体集成电子电路的制造方法，其特征在于，在基板上形成辅助层， 在辅助层上沉积一层筛选材料; 选择性地去除所述筛选材料层以在所述筛选材料层中提供第一开口并暴露所述辅助层的区域; 并且去除辅助层的该区域以在辅助层中形成第二开口，其横截面朝向衬底变窄，以暴露衬底的区域小于由第一开口暴露的区域。

公开(公告)号：US06638833B1

公开(公告)日：2003-10-28

申请号：US09804693

申请日：2001-03-09

申请人： Omar Vassalli ,  Simone Alba

发明人： Omar Vassalli ,  Simone Alba

IPC分类号： H01L2176

CPC分类号： H01L21/31144 ,  H01L21/0273 ,  H01L21/0332 ,  Y10S438/942

摘要： The process for the fabrication of an electronic device has the steps of forming a layer to be etched on top of a substrate in a wafer of semiconductor material; depositing a masking layer; and carrying out a plasma etch to define the geometry of the layer to be etched. The masking layer is made so as to be conductive, at least during one part of the etching step; in this way, the electrons implanted on the top part of the masking layer during plasma etching can recombine with the positive charges which have reached the layer to be etched. The recombination of the charges makes it possible to prevent damage from plasma resulting from the formation of parasitic electric currents which are detrimental to the electronic device itself.

摘要翻译： 制造电子器件的方法具有以下步骤：在半导体材料的晶片中形成待蚀刻的层在衬底的顶部; 沉积掩模层; 并进行等离子体蚀刻以限定待蚀刻层的几何形状。 至少在蚀刻步骤的一部分期间，将掩模层制成为导电的; 以这种方式，在等离子体蚀刻期间注入掩模层顶部的电子可以与已经达到待蚀刻层的正电荷重新组合。 电荷的复合使得可以防止由于形成对电子器件本身有害的寄生电流而导致的等离子体损伤。

公开(公告)号：US5888836A

公开(公告)日：1999-03-30

申请号：US990328

申请日：1997-12-15

申请人： Emilio Ghio ,  Simone Alba ,  Andrea Colognese

发明人： Emilio Ghio ,  Simone Alba ,  Andrea Colognese

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/268

CPC分类号： H01L29/66825 ,  H01L21/28176

摘要： The process described requires the formation of floating-gate non-volatile memory cells entirely similar in structure to those produced by known processes. The process comprises an annealing treatment at relatively low temperature (430.degree. C.) to repair damage due to plasma treatments. To obtain threshold voltage values for the cells close to the theoretical values, especially for cells with particularly extended interconnections, the cells are subjected to ultraviolet radiation before the annealing treatment, in order to neutralize any electrical charges present in the floating-gate electrodes of the cells.

摘要翻译： 所描述的方法需要形成与已知方法制造的那些结构完全相似的浮栅非易失性存储单元。 该方法包括在较低温度（430℃）下进行退火处理，以修复等离子体处理造成的损坏。 为了获得接近理论值的电池的阈值电压值，特别是对于具有特别延长的互连的电池，在退火处理之前对电池进行紫外线辐射，以便中和存在于浮栅电极中的任何电荷 细胞。

公开(公告)号：US07288427B2

公开(公告)日：2007-10-30

申请号：US11009687

申请日：2004-12-10

申请人： Simone Alba ,  Alessandro Spandre ,  Barbara Zanderighi

发明人： Simone Alba ,  Alessandro Spandre ,  Barbara Zanderighi

IPC分类号： H01L21/00

CPC分类号： H01L21/76801 ,  H01L21/0332 ,  H01L21/32139 ,  H01L21/76834 ,  H01L21/76838

摘要： The method prevents oxidation or contamination phenomena of conductive interconnection structures in semiconductor devices and includes providing a layer of semiconductor or oxide base, a conductive layer or stack on the base layer, and an antireflection coating (ARC) layer on the conductive layer or stack. The method provides a thin dielectric covering layer on the antireflection coating layer to fill or cover the microfissures existing in the antireflection coating layer.

摘要翻译： 该方法防止半导体器件中的导电互连结构的氧化或污染现象，并且包括在基底层上提供半导体层或氧化物层，导电层或叠层，以及导电层或叠层上的抗反射涂层（ARC）层。 该方法在抗反射涂层上提供薄的电介质覆盖层，以填充或覆盖存在于抗反射涂层中的微裂缝。

公开(公告)号：US20050186780A1

公开(公告)日：2005-08-25

申请号：US11009687

申请日：2004-12-10

申请人： Simone Alba ,  Alessandro Spandre ,  Barbara Zanderighi

发明人： Simone Alba ,  Alessandro Spandre ,  Barbara Zanderighi

IPC分类号： H01L21/033 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/44 ,  H01L21/768

CPC分类号： H01L21/76801 ,  H01L21/0332 ,  H01L21/32139 ,  H01L21/76834 ,  H01L21/76838

摘要： The method prevents oxidation or contamination phenomena of conductive interconnection structures in semiconductor devices and includes providing a layer of semiconductor or oxide base, a conductive layer or stack on the base layer, and an antireflection coating (ARC) layer on the conductive layer or stack. The method provides a thin dielectric covering layer on the antireflection coating layer to fill or cover the microfissures existing in the antireflection coating layer.

摘要翻译： 该方法防止半导体器件中的导电互连结构的氧化或污染现象，并且包括在基底层上提供半导体层或氧化物层，导电层或叠层，以及导电层或叠层上的抗反射涂层（ARC）层。 该方法在抗反射涂层上提供薄的电介质覆盖层，以填充或覆盖存在于抗反射涂层中的微裂缝。

公开(公告)号：US20050037500A1

公开(公告)日：2005-02-17

申请号：US10652862

申请日：2003-08-29

申请人： Francesco Ciovacco ,  Fabio Somboli ,  Giuseppe Fazio ,  Simone Alba

发明人： Francesco Ciovacco ,  Fabio Somboli ,  Giuseppe Fazio ,  Simone Alba

IPC分类号： H01J37/32 ,  G01N21/00

CPC分类号： H01J37/3244

摘要： A method (300) and a corresponding apparatus for detecting a leak of external air into a plasma reactor are proposed. The method includes: establishing (340) a plasma inside the reactor, the plasma having a composition suitable to generate at least one predetermined compound when reacting with the air, detecting (345) a light emission of the plasma, and analyzing (350-375) the light emission to identify the presence of the at least one predetermined compound.

摘要翻译： 提出了一种用于检测外部空气泄漏到等离子体反应器中的方法（300）和相应的装置。 该方法包括：在反应器内建立（340）等离子体，所述等离子体具有适合于在与空气反应时产生至少一种预定化合物的组合物，检测（345）等离子体的发光并分析（350-375 ）发光以识别至少一种预定化合物的存在。

公开(公告)号：US06495455B2

公开(公告)日：2002-12-17

申请号：US09836937

申请日：2001-04-17

申请人： Omar Vassalli ,  Simone Alba

发明人： Omar Vassalli ,  Simone Alba

IPC分类号： H01L2144

CPC分类号： H01L21/32136 ,  H01L21/32139

摘要： A method enhances selectivity between a film of a light-sensitive material and a layer to be subjected to etching in the course of fabrication processes of an electronic semiconductor device starting from a semiconductor material wafer. The method includes radiating the wafer with an ion beam subsequently to depositing the layer to be etched and defining a circuit pattern on the film of light-sensitive material. An alternative method exposes the wafer to a non-reactive gas medium under plasma rather than radiating the wafer with an ion beam.

摘要翻译： 在从半导体材料晶片开始的电子半导体器件的制造过程中，一种方法提高了感光材料的膜和要进行蚀刻的层之间的选择性。 该方法包括随后沉积待蚀刻的层并且在感光材料的膜上限定电路图案，用离子束辐射晶片。 另一种方法是将晶片暴露在等离子体下的非反应性气体介质中，而不是用离子束辐射晶片。