公开(公告)号：US5811997A

公开(公告)日：1998-09-22

申请号：US638186

申请日：1996-04-26

Applicant: David P. Chengson ,  Robert A. Conrad

Inventor： David P. Chengson ,  Robert A. Conrad

IPC: H03K19/0185 ,  H03K19/173 ,  H03K11/007

CPC classification number: H03K19/018585 ,  H03K19/1736

Abstract: A multi-configurable HSTL/LVCMOS/Open-Drain output driver circuit includes push-pull and open-drain transistors that are selectively enabled/disabled depending upon the desired mode of operation.

Abstract translation: 多组态HSTL / LVCMOS /漏极开路输出驱动电路包括根据所需的工作模式选择性地使能/禁止的推挽和开漏晶体管。

公开(公告)号：US5710733A

公开(公告)日：1998-01-20

申请号：US589532

申请日：1996-01-22

Applicant: David P. Chengson ,  William L. Schmidt ,  Unmesh Agarwala ,  Alan D. Foster ,  Edward C. Priest ,  John C. Manton ,  Ali Mira

Inventor： David P. Chengson ,  William L. Schmidt ,  Unmesh Agarwala ,  Alan D. Foster ,  Edward C. Priest ,  John C. Manton ,  Ali Mira

IPC: G06F15/78 ,  G11C5/00 ,  H01L25/18 ,  H05K7/14 ,  H03H11/00 ,  H05K7/02

CPC classification number: H05K7/1422 ,  G06F15/7864 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: A processor-inclusive memory module (PIMM) is disclosed. In one embodiment of the present invention, the PIMM includes a printed circuit board having first and second opposing surfaces. The printed circuit board also has an address line formed therein. A first SRAM is mounted on the first surface of the printed circuit board. The present PIMM is further comprised of a second SRAM mounted on the second surface of the printed circuit board. The second SRAM is mounted on the second surface of the printed circuit board directly opposite the first SRAM mounted on the first surface of the printed circuit board. The first and second SRAMs are coupled to the address line by respective cache buses. A processor is also mounted on the first surface of the printed circuit board, and is coupled to the address line. In one embodiment of the invention, a heat sink is thermally coupled to the processor. The processor has a plurality of contact pads disposed thereon. Electrical connectors extend from the second surface of the printed circuit board. The electrical connectors are electrically coupled to respective contact pads of the processor. In the present PIMM, the electrical connectors are adapted to be removably attached to a mother board. In so doing, the present PIMM is removably attachable to a mother board.

公开(公告)号：US4728818A

公开(公告)日：1988-03-01

申请号：US942669

申请日：1986-12-17

Applicant: David P. Chengson ,  Aurangzeb K. Khan

Inventor： David P. Chengson ,  Aurangzeb K. Khan

IPC: H03K3/286 ,  H03K3/2885 ,  H03K19/086 ,  H03K3/284 ,  H03K3/29

CPC classification number: H03K3/2885 ,  H03K19/0863

Abstract: An improved EFL gate which provides concurrent true and complementary outputs. An input transistor has its base coupled to an input and its emitter coupled to an emitter of a reference transistor. The reference transistor has its base coupled to a voltage reference and its collector coupled to the base of a true output transistor. The emitter of the true output transistor provides the true output, while its collector is coupled to a voltage supply. A complementary output transistor has its base coupled to the collector of the input transistor with its emitter providing the complementary output. Its collector is coupled to the voltage supply, as is the collector of the input transistor.

公开(公告)号：US08411695B1

公开(公告)日：2013-04-02

申请号：US11134256

申请日：2005-05-23

Applicant: David P. Chengson ,  Jaya Bandyopadhyay

Inventor： David P. Chengson ,  Jaya Bandyopadhyay

IPC: H04L12/28

CPC classification number: H04J3/06 ,  G06F13/4022 ,  H04J3/0697 ,  H04L7/0008

Abstract: A multi-interface bus allows for different bus standards to be implemented over the same set of physical bus lines. More particularly, in one implementation, the system includes a first circuit board, a second circuit board, and a bus connecting the first and second circuit boards. The second circuit board is configured to communicate with the first circuit board using either a synchronous or an asynchronous bus protocol determined based on a bus protocol used by the first circuit board.

Abstract translation: 多接口总线允许在同一组物理总线上实现不同的总线标准。 更具体地，在一个实施方式中，该系统包括第一电路板，第二电路板和连接第一和第二电路板的总线。 第二电路板被配置为使用基于由第一电路板使用的总线协议确定的同步或异步总线协议与第一电路板通信。

公开(公告)号：US5041747A

公开(公告)日：1991-08-20

申请号：US889439

申请日：1986-07-23

Applicant: David P. Chengson ,  H. William Wang

Inventor： David P. Chengson ,  H. William Wang

IPC: G05F1/46 ,  H03K19/003 ,  H03K19/086

CPC classification number: H03K19/086 ,  G05F1/466 ,  H03K19/00323

Abstract: An integrated circuit chip carries a number of electronic circuits, at least one of which includes, in its output stage, a control device that responds to a reference signal to adjust the output current-handling capability of the electronic circuit, thereby regulating the signal propagation delay exhibited by the electronic circuit. The reference circuit is generated by a digital-to-analog circuit that is also formed on the chip. The digital-to-analog circuit is coupled to a number of contact elements disposed on an outer surface of the package containing the integrated circuit chip that can be selectively interconnected to a DC voltage to choose the value of the reference signal.

Abstract translation: 集成电路芯片承载多个电子电路，其中至少一个在其输出级中包括响应参考信号以调整电子电路的输出电流处理能力的控制装置，从而调节信号传播 延迟由电子电路表现出来。 参考电路由也在芯片上形成的数模转换电路产生。 数模转换电路耦合到多个接触元件，该接触元件设置在包含集成电路芯片的封装的外表面上，该集成电路芯片可选择性地互连到直流电压以选择参考信号的值。