公开(公告)号：US07298949B2

公开(公告)日：2007-11-20

申请号：US11042774

申请日：2005-01-24

申请人： Prakash Gothoskar ,  Margaret Ghiron ,  Robert Keith Montgomery ,  Vipulkumar Patel ,  Soham Pathak ,  David Piede ,  Kalpendu Shastri ,  Katherine A. Yanushefski

发明人： Prakash Gothoskar ,  Margaret Ghiron ,  Robert Keith Montgomery ,  Vipulkumar Patel ,  Soham Pathak ,  David Piede ,  Kalpendu Shastri ,  Katherine A. Yanushefski

IPC分类号： G02B6/10 ,  G02B6/12

CPC分类号： G02F1/025 ,  G02F2202/32

摘要： An SOI-based photonic bandgap (PBG) electro-optic device utilizes a patterned PBG structure to define a two-dimensional waveguide within an active waveguiding region of the SOI electro-optic device. The inclusion of the PBG columnar arrays within the SOI structure results in providing extremely tight lateral confinement of the optical mode within the waveguiding structure, thus significantly reducing the optical loss. By virtue of including the PBG structure, the associated electrical contacts may be placed in closer proximity to the active region without affecting the optical performance, thus increasing the switching speed of the electro-optic device. The overall device size, capacitance and resistance are also reduced as a consequence of using PBGs for lateral mode confinement.

摘要翻译： 基于SOI的光子带隙（PBG）电光器件利用图案化的PBG结构来在SOI电光器件的有源波导区域内限定二维波导。 在SOI结构中包含PBG柱状阵列导致在波导结构内提供光学模式的非常紧密的侧向约束，从而显着减少光学损耗。 通过包括PBG结构，相关联的电触点可以放置在更接近有源区域而不影响光学性能，从而增加电光器件的切换速度。 由于使用PBG用于横向模式限制，整个装置尺寸，电容和电阻也减小。

公开(公告)号：US07657130B2

公开(公告)日：2010-02-02

申请号：US12287366

申请日：2008-10-08

申请人： Kalpendu Shastri ,  Prakash Gothoskar ,  Vipulkumar Patel ,  David Piede ,  Mark Webster

发明人： Kalpendu Shastri ,  Prakash Gothoskar ,  Vipulkumar Patel ,  David Piede ,  Mark Webster

IPC分类号： G02F1/035 ,  G02F1/01 ,  G02B6/12

CPC分类号： G02F1/0121 ,  G02F1/2255 ,  G02F1/2257 ,  G02F2001/0152

摘要： A silicon-insulator-silicon capacitive (SISCAP) optical modulator is configured to provide analog operation for applications which previously required the use of relatively large, power-consuming and expensive lithium niobate devices. An MZI-based SISCAP modulator (preferably a balanced arrangement with a SISCAP device on each arm) is responsive to an incoming high frequency electrical signal and is biased in a region where the capacitance of the device is essentially constant and the transform function of the MZI is linear.

摘要翻译： 硅 - 绝缘体 - 硅电容（SISCAP）光调制器被配置为为先前需要使用相对较大，耗电和昂贵的铌酸锂器件的应用提供模拟操作。 基于MZI的SISCAP调制器（优选地，在每个臂上具有SISCAP器件的平衡布置）响应于输入的高频电信号，并且被偏置在器件的电容基本上恒定的区域中，并且MZI的变换函数 是线性的

公开(公告)号：US07358585B2

公开(公告)日：2008-04-15

申请号：US10990725

申请日：2004-11-17

申请人： Vipulkumar Patel ,  Margaret Ghiron ,  Prakash Gothoskar ,  Robert Keith Montgomery ,  Soham Pathak ,  David Piede ,  Kalpendu Shastri ,  Katherine A. Yanushefski

发明人： Vipulkumar Patel ,  Margaret Ghiron ,  Prakash Gothoskar ,  Robert Keith Montgomery ,  Soham Pathak ,  David Piede ,  Kalpendu Shastri ,  Katherine A. Yanushefski

IPC分类号： G02B6/10 ,  H01L31/0224

CPC分类号： H01L31/108 ,  G02B6/12004 ,  G02B6/1228 ,  H01L31/022408 ,  H01L31/0232 ,  H01L31/03921 ,  H01L31/153 ,  Y02E10/50

摘要： A silicon-based IR photodetector is formed within a silicon-on-insulator (SOI) structure by placing a metallic strip (preferably, a silicide) over a portion of an optical waveguide formed within a planar silicon surface layer (i.e., “planar SOI layer”) of the SOI structure, the planar SOI layer comprising a thickness of less than one micron. Room temperature operation of the photodetector is accomplished as a result of the relatively low dark current associated with the SOI-based structure and the ability to use a relatively small surface area silicide strip to collect the photocurrent. The planar SOI layer may be doped, and the geometry of the silicide strip may be modified, as desired, to achieve improved results over prior art silicon-based photodetectors.

摘要翻译： 通过将金属条（优选硅化物）放置在形成在平面硅表面层内的光波导的一部分（即，“平面SOI”）上，在绝缘体上硅（SOI）结构中形成硅基红外光电检测器 层“），平面SOI层包括小于1微米的厚度。 由于与基于SOI的结构相关联的相对较低的暗电流和使用相对小的表面积硅化物带收集光电流的能力，光电检测器的室温操作是完成的。 可以掺杂平面SOI层，并且根据需要可以修改硅化物带的几何形状，以实现相对于现有技术的硅基光电探测器的改进的结果。

公开(公告)号：US07113676B2

公开(公告)日：2006-09-26

申请号：US11005286

申请日：2004-12-06

申请人： David Piede ,  Margaret Ghiron ,  Prakash Gothoskar ,  Robert Keith Montgomery ,  Vipulkumar Patel ,  Kalpendu Shastri ,  Soham Pathak ,  Katherine A. Yanushefski ,  Harvey Wagner

发明人： David Piede ,  Margaret Ghiron ,  Prakash Gothoskar ,  Robert Keith Montgomery ,  Vipulkumar Patel ,  Kalpendu Shastri ,  Soham Pathak ,  Katherine A. Yanushefski ,  Harvey Wagner

IPC分类号： G02B6/26 ,  G02B6/42

CPC分类号： G02B6/1228 ,  G02B6/125 ,  G02B6/4207

摘要： A planar optical isolator is formed within the silicon surface layer of an SOI structure. A forward-directed signal is applied to an input waveguiding section of the isolator and thereafter propagates through a non-reciprocal waveguide coupling region into an output waveguide section. A rearward-directed signal enters via the output waveguide section and is thereafter coupled into the non-reciprocal waveguide structure, where the geometry of the structure functions to couple only a small amount of the reflected signal into the input waveguide section. In one embodiment, the non-reciprocal structure comprises an N-way directional coupler (with one output waveguide, one input waveguide and N−1 isolating waveguides). In another embodiment, the non-reciprocal structure comprises a waveguide expansion region including a tapered, mode-matching portion coupled to the output waveguide and an enlarged, non-mode matching portion coupled to the input waveguide such that a majority of a reflected signal will be mismatched with respect to the input waveguide section. By cascading a number of such planar SOI-based structures, increased isolation can be achieved—advantageously within a monolithic arrangement.

摘要翻译： 在SOI结构的硅表面层内形成平面光隔离器。 正向信号被施加到隔离器的输入波导部分，然后通过非互易波导耦合区域传播到输出波导部分中。 后向信号经由输出波导部分进入，然后耦合到不可逆波导结构中，其中结构的几何结构仅将少量的反射信号耦合到输入波导部分中。 在一个实施例中，非互易结构包括N路定向耦合器（具有一个输出波导，一个输入波导和N-1个隔离波导）。 在另一个实施例中，不可逆结构包括波导扩展区域，其包括耦合到输出波导的锥形模式匹配部分和耦合到输入波导的放大的非模式匹配部分，使得反射信号的大部分将 相对于输入波导部分不匹配。 通过级联多个这种平面的基于SOI的结构，可以实现增加的隔离 - 有利地在单片布置中。

公开(公告)号：US07109739B2

公开(公告)日：2006-09-19

申请号：US11075430

申请日：2005-03-08

申请人： Prakash Gothoskar ,  Margaret Ghiron ,  Robert Keith Montgomery ,  Vipulkumar Patel ,  Kalpendu Shastri ,  Soham Pathak ,  David Piede ,  Katherine A. Yanushefski

发明人： Prakash Gothoskar ,  Margaret Ghiron ,  Robert Keith Montgomery ,  Vipulkumar Patel ,  Kalpendu Shastri ,  Soham Pathak ,  David Piede ,  Katherine A. Yanushefski

IPC分类号： G01R31/26 ,  G01R31/00

CPC分类号： G02B6/30 ,  G02B6/34 ,  G02B2006/12107

摘要： A wafer-level testing arrangement for opto-electronic devices formed in a silicon-on-insulator (SOI) wafer structure utilizes a single opto-electronic testing element to perform both optical and electrical testing. Beam steering optics may be formed on the testing element and used to facilitate the coupling between optical probe signals and optical coupling elements (e.g., prism couplers, gratings) formed on the top surface of the SOI structure. The optical test signals are thereafter directed into optical waveguides formed in the top layer of the SOI structure. The opto-electronic testing element also comprises a plurality of electrical test pins that are positioned to contact a plurality of bondpad test sites on the opto-electronic device and perform electrical testing operations. The optical test signal results may be converted into electrical representations within the SOI structure and thus returned to the testing element as electrical signals.

摘要翻译： 用于在绝缘体上硅（SOI）晶片结构中形成的光电器件的晶片级测试装置利用单个光电测试元件执行光学和电学测试。 光束转向光学元件可以形成在测试元件上，并且用于促进光学探针信号与形成在SOI结构的顶表面上的光耦合元件（例如，棱镜耦合器，光栅）之间的耦合。 此后，光学测试信号被引导到形成在SOI结构的顶层中的光波导中。 光电测试元件还包括多个电测试引脚，其被定位成接触光电器件上的多个接合焊盘测试点并执行电测试操作。 光学测试信号结果可以转换为SOI结构内的电气表示，并因此作为电信号返回到测试元件。

公开(公告)号：US20090162013A1

公开(公告)日：2009-06-25

申请号：US12316540

申请日：2008-12-11

申请人： Mark Webster ,  Vipulkumar Patel ,  Mary Nadeau ,  Prakash Gothoskar ,  David Piede

发明人： Mark Webster ,  Vipulkumar Patel ,  Mary Nadeau ,  Prakash Gothoskar ,  David Piede

IPC分类号： G02B6/42

CPC分类号： G02B6/32 ,  G02B6/305 ,  G02B6/327

摘要： A plasma-based etching process is used to specifically shape the endface of an optical substrate supporting an optical waveguide into a contoured facet which will improve coupling efficiency between the waveguide and a free space optical signal. The ability to use standard photolithographic techniques to pattern and etch the optical endface facet allows for virtually any desired facet geometry to be formed—and replicated across the surface of a wafer for the entire group of assemblies being fabricated. A lens may be etched into the endface using a properly-defined photolithographic mask, with the focal point of the lens selected with respect to the parameters of the optical waveguide and the propagating free space signal. Alternatively, an angled facet may be formed along the endface, with the angle sufficient to re-direct reflected/scattered signals away from the optical axis.

摘要翻译： 使用基于等离子体的蚀刻工艺来将支撑光波导的光学基板的端面特别地成形为轮廓刻面，这将提高波导与自由空间光信号之间的耦合效率。 使用标准光刻技术对光学端面小平面进行图案化和刻蚀的能力允许形成任何所需的刻面几何形状，并跨越制造的整组组件在晶片的表面上复制。 可以使用适当限定的光刻掩模将透镜蚀刻到端面中，相对于光波导的参数和传播的自由空间信号选择透镜的焦点。 或者，可以沿着端面形成成角度的小面，其角度足以将反射/散射信号重新引导远离光轴。

公开(公告)号：US08121450B2

公开(公告)日：2012-02-21

申请号：US12316540

申请日：2008-12-11

申请人： Mark Webster ,  Vipulkumar Patel ,  Mary Nadeau ,  Prakash Gothoskar ,  David Piede

发明人： Mark Webster ,  Vipulkumar Patel ,  Mary Nadeau ,  Prakash Gothoskar ,  David Piede

IPC分类号： G02B6/32 ,  G02B6/26 ,  G02B6/42

CPC分类号： G02B6/32 ,  G02B6/305 ,  G02B6/327

摘要： A plasma-based etching process is used to specifically shape the endface of an optical substrate supporting an optical waveguide into a contoured facet which will improve coupling efficiency between the waveguide and a free space optical signal. The ability to use standard photolithographic techniques to pattern and etch the optical endface facet allows for virtually any desired facet geometry to be formed—and replicated across the surface of a wafer for the entire group of assemblies being fabricated. A lens may be etched into the endface using a properly-defined photolithographic mask, with the focal point of the lens selected with respect to the parameters of the optical waveguide and the propagating free space signal. Alternatively, an angled facet may be formed along the endface, with the angle sufficient to re-direct reflected/scattered signals away from the optical axis.

摘要翻译： 使用基于等离子体的蚀刻工艺来将支撑光波导的光学基板的端面特别地成形为轮廓刻面，这将提高波导与自由空间光信号之间的耦合效率。 使用标准光刻技术对光学端面小平面进行图案化和刻蚀的能力允许形成任何所需的刻面几何形状，并跨越制造的整组组件在晶片的表面上复制。 可以使用适当限定的光刻掩模将透镜蚀刻到端面中，相对于光波导的参数和传播的自由空间信号选择透镜的焦点。 或者，可以沿着端面形成成角度的小面，其角度足以将反射/散射信号重新引导远离光轴。

公开(公告)号：US20060177173A1

公开(公告)日：2006-08-10

申请号：US11346718

申请日：2006-02-03

申请人： Kalpendu Shastri ,  Vipulkumar Patel ,  David Piede ,  John Fangman

发明人： Kalpendu Shastri ,  Vipulkumar Patel ,  David Piede ,  John Fangman

IPC分类号： G02B6/12 ,  G02B6/26 ,  G02B6/42 ,  G02B6/10

CPC分类号： G02B6/42 ,  G02B6/4214 ,  G02B6/43 ,  G02F1/025 ,  H01L31/12

摘要： A vertical stack of integrated circuits includes at least one CMOS electronic integrated circuit (IC), an SOI-based opto-electronic integrated circuit structure, and an optical input/output coupling element. A plurality of metalized vias may be formed through the thickness of the stack so that electrical connections can be made between each integrated circuit. Various types of optical input/output coupling can be used, such as prism coupling, gratings, inverse tapers, and the like. By separating the optical and electrical functions onto separate ICs, the functionalities of each may be modified without requiring a re-design of the remaining system. By virtue of using SOI-based opto-electronics with the CMOS electronic ICs, a portion of the SOI structure may be exposed to provide access to the waveguiding SOI layer for optical coupling purposes.

摘要翻译： 集成电路的垂直堆叠包括至少一个CMOS电子集成电路（IC），基于SOI的光电集成电路结构以及光输入/输出耦合元件。 可以通过堆叠的厚度形成多个金属化通孔，使得可以在每个集成电路之间进行电连接。 可以使用各种类型的光输入/输出耦合，例如棱镜耦合，光栅，逆锥等。 通过将光学和电气功能分离到单独的IC上，可以修改每个功能，而不需要重新设计剩余的系统。 通过使用具有CMOS电子IC的基于SOI的光电子器件，SOI结构的一部分可能被暴露以提供对波导SOI层的访问以用于光学耦合目的。

公开(公告)号：US07706644B2

公开(公告)日：2010-04-27

申请号：US12218367

申请日：2008-07-15

申请人： Mark Webster ,  Prakash Gothoskar ,  Vipulkumar Patel ,  David Piede

发明人： Mark Webster ,  Prakash Gothoskar ,  Vipulkumar Patel ,  David Piede

IPC分类号： G02B6/26

CPC分类号： G02B6/30 ,  G02B6/3598 ,  G02B6/3636 ,  G02B6/3652 ,  G02B6/3692 ,  G02B6/4249

摘要： One or more nanotaper coupling waveguides formed within an optical substrate allows for straightforward, reproducible offset launch conditions to be achieved between an incoming signal and the core region of a multimode fiber (which may be disposed along an alignment fixture formed in the optical substrate), fiber array or other multimode waveguiding structure. Offset launching of a single mode signal into a multimode fiber couples the signal into favorable spatial modes which reduce the presence of differential mode dispersion along the fiber. This approach to providing single mode signal coupling into legacy multimode fiber is considered to be an improvement over the prior art which required the use of an interface element between a single mode fiber and multimode fiber, limiting the number of propagating signals and applications for the legacy multimode fiber. An optical switch may be used to select the specific nanotaper(s) for coupling into the multimode fiber.

摘要翻译： 形成在光学衬底内的一个或多个纳米锥耦合波导允许在多模光纤（其可以沿着形成在光学衬底中的对准夹具设置）的入射信号和芯区域之间实现简单，可再现的偏移发射条件， 光纤阵列或其他多模波导结构。 偏移将单模信号发射到多模光纤中将信号耦合到有利的空间模式，这降低了沿着光纤的差分色散的存在。 将单模信号耦合提供给传统多模光纤的这种方法被认为是对需要使用单模光纤和多模光纤之间的接口元件的现有技术的改进，限制了传播信号的数量和遗留的应用 多模光纤 可以使用光学开关来选择用于耦合到多模光纤的特定纳米锥。

公开(公告)号：US20110222812A1

公开(公告)日：2011-09-15

申请号：US13029342

申请日：2011-02-17

申请人： Mark Webster ,  Vipulkumar Patel ,  Prakash Gothoskar ,  David Piede

发明人： Mark Webster ,  Vipulkumar Patel ,  Prakash Gothoskar ,  David Piede

IPC分类号： G02F1/01

CPC分类号： G02B6/12 ,  G02B6/26 ,  G02B26/00 ,  G02F1/025

摘要： A high speed silicon-based optical modulator with control of the dopant profiles in the body and gate regions of the device reduces the series resistance of the structure without incurring substantial optical power loss. That is, the use of increased dopant values in areas beyond the active region will allow for the series resistance to be reduced (and thus increase the modulating speed of the device) without incurring too large a penalty in signal loss. The dopant profiles within the gate and body regions are tailored to exhibit an intermediate value between the high dopant concentration in the contact areas and the low dopant concentration in the carrier integration window area.

摘要翻译： 具有控制器件的主体和栅极区域中的掺杂剂分布的高速硅基光学调制器降低了结构的串联电阻而不会引起实质的光功率损耗。 也就是说，在有源区域之外的区域中使用增加的掺杂剂值将允许降低串联电阻（从而增加器件的调制速度），而不会在信号损失中造成太大的惩罚。 调整栅极和体区内的掺杂剂分布，以显示接触区域中的高掺杂剂浓度与载流子集成窗口区域中的低掺杂剂浓度之间的中间值。