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公开(公告)号：US20110272779A1
公开(公告)日：2011-11-10
申请号：US13189016
申请日：2011-07-22
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.
摘要翻译： eFuse包括：衬底和设置在衬底上的绝缘层; 包括设置在所述绝缘层上的单晶或多晶硅的第一层; 包括设置在第一层上的单晶或多晶硅锗的第二层，以及包括设置在第二层上的硅化物的第三层。 Ge的终浓度范围约为百分之五至百分之二十五。
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12.发明授权Electrical fuse having a fully silicided fuselink and enhanced flux divergence 有权电熔丝具有完全硅化的富熔体和增强的焊剂分散公开(公告)号：US07943493B2
公开(公告)日：2011-05-17
申请号：US12873882
申请日：2010-09-01
IPC分类号： H01L21/20
CPC分类号： H01L23/5256 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to a lower semiconductor layer in the exposed portion. The etch mask is removed and the entirety of the lower semiconductor layer within the exposed region is metallized. A first metal semiconductor alloy vertically abutting the insulator region is formed, while exposed surfaces of the stack of two heterogeneous semiconductor layers, which comprises the materials of the upper semiconductor layer, are concurrently metallized to form a second metal semiconductor alloy. An inflection point for current and, consequently, a region of flux divergence are formed at the boundary of the two metal semiconductor alloys.
摘要翻译： 在绝缘体区域上形成两个不均匀半导体层的堆叠的连续块，例如浅沟槽隔离。 连续块的一部分暴露于蚀刻，而另一部分在蚀刻期间被掩蔽。 蚀刻去除在暴露部分中对下半导体层有选择性的上半导体层。 去除蚀刻掩模，并且暴露区域内的下半导体层的整体被金属化。 形成垂直邻接绝缘体区域的第一金属半导体合金，同时将包含上半导体层的材料的两个非均匀半导体层的堆叠的暴露表面同时金属化以形成第二金属半导体合金。 在两个金属半导体合金的边界处形成电流的拐点，从而形成磁通发散区域。
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13.发明申请ELECTRICAL FUSE HAVING A FULLY SILICIDED FUSELINK AND ENHANCED FLUX DIVERGENCE 有权全自动充电式电熔炉和增强型流量分流器公开(公告)号：US20100330783A1
公开(公告)日：2010-12-30
申请号：US12873882
申请日：2010-09-01
IPC分类号： H01L21/20
CPC分类号： H01L23/5256 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to a lower semiconductor layer in the exposed portion. The etch mask is removed and the entirety of the lower semiconductor layer within the exposed region is metallized. A first metal semiconductor alloy vertically abutting the insulator region is formed, while exposed surfaces of the stack of two heterogeneous semiconductor layers, which comprises the materials of the upper semiconductor layer, are concurrently metallized to form a second metal semiconductor alloy. An inflection point for current and, consequently, a region of flux divergence are formed at the boundary of the two metal semiconductor alloys.
摘要翻译： 在绝缘体区域上形成两个不均匀半导体层的堆叠的连续块，例如浅沟槽隔离。 连续块的一部分暴露于蚀刻，而另一部分在蚀刻期间被掩蔽。 蚀刻去除在暴露部分中对下半导体层有选择性的上半导体层。 去除蚀刻掩模，并且暴露区域内的下半导体层的整体被金属化。 形成垂直邻接绝缘体区域的第一金属半导体合金，同时将包含上半导体层的材料的两个非均匀半导体层的堆叠的暴露表面同时金属化以形成第二金属半导体合金。 在两个金属半导体合金的边界处形成电流的拐点，从而形成磁通发散区域。
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公开(公告)号：US07745855B2
公开(公告)日：2010-06-29
申请号：US11867268
申请日：2007-10-04
IPC分类号： H01L27/10
CPC分类号： H01L23/5256 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： An integrated eFUSE device is formed by forming a silicon “floating beam” on air, whereupon the fusible portion of the eFUSE device resides. This beam extends between two larger, supporting terminal structures. “Undercutting” techniques are employed whereby a structure is formed atop a buried layer, and that buried layer is removed by selective etching. Whereby a “floating” silicide eFUSE conductor is formed on a silicon beam structure. In its initial state, the eFUSE silicide is highly conductive, exhibiting low electrical resistance (the “unblown state of the eFUSE). When a sufficiently large current is passed through the eFUSE conductor, localized heating occurs. This heating causes electromigration of the silicide into the silicon beam (and into surrounding silicon, thereby diffusing the silicide and greatly increasing its electrical resistance. When the current source is removed, the silicide remains permanently in this diffused state, the “blown” state of the eFUSE.
摘要翻译： 通过在空气中形成硅“浮动光束”形成集成eFUSE装置，于是eFUSE装置的可熔部分驻留。 该梁在两个较大的支撑端子结构之间延伸。 采用“底切”技术，由此在掩埋层顶部形成结构，并且通过选择性蚀刻去除掩埋层。 由此在硅梁结构上形成“浮动”硅化物eFUSE导体。 在其初始状态下，eFUSE硅化物具有高导电性，表现出低电阻（eFUSE的未吹出状态）。 当足够大的电流通过eFUSE导体时，发生局部加热。 这种加热导致硅化物的电迁移到硅束（并进入周围的硅，从而扩散硅化物，并大大增加其电阻。当电流源被去除时，硅化物永久地保持在这种扩散状态，“吹”状态 eFUSE。
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公开(公告)号：US20090090993A1
公开(公告)日：2009-04-09
申请号：US11867268
申请日：2007-10-04
CPC分类号： H01L23/5256 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： An integrated eFUSE device is formed by forming a silicon “floating beam” on air, whereupon the fusible portion of the eFUSE device resides. This beam extends between two larger, supporting terminal structures. “Undercutting” techniques are employed whereby a structure is formed atop a buried layer, and that buried layer is removed by selective etching. Whereby a “floating” silicide eFUSE conductor is formed on a silicon beam structure. In its initial state, the eFUSE silicide is highly conductive, exhibiting low electrical resistance (the “unblown state of the eFUSE). When a sufficiently large current is passed through the eFUSE conductor, localized heating occurs. This heating causes electromigration of the silicide into the silicon beam (and into surrounding silicon, thereby diffusing the silicide and greatly increasing its electrical resistance. When the current source is removed, the silicide remains permanently in this diffused state, the “blown” state of the eFUSE.
摘要翻译： 通过在空气中形成硅“浮动光束”形成集成eFUSE装置，于是eFUSE装置的可熔部分驻留。 该梁在两个更大的支撑端子结构之间延伸。 采用“底切”技术，由此在掩埋层顶部形成结构，并且通过选择性蚀刻去除掩埋层。 由此在硅梁结构上形成“浮动”硅化物eFUSE导体。 在初始状态下，eFUSE硅化物具有高导电性，表现出较低的电阻（eFUSE的未吹出状态），当足够大的电流通过eFUSE导体时，发生局部加热，该加热导致硅化物的电迁移 （并且进入周围的硅，从而扩散硅化物并大大增加其电阻。当电流源被去除时，硅化物永久地保持在这种扩散状态，eFUSE的“吹”状态。
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公开(公告)号：US07750335B2
公开(公告)日：2010-07-06
申请号：US11839724
申请日：2007-08-16
申请人： Lawrence A. Clevenger , Bruce G. Elmegreen , Deok-Kee Kim , Chandrasekharan Kothandaraman , Lia Krusin-Elbaum , Chung H. Lam , Dennis M. Newns
发明人： Lawrence A. Clevenger , Bruce G. Elmegreen , Deok-Kee Kim , Chandrasekharan Kothandaraman , Lia Krusin-Elbaum , Chung H. Lam , Dennis M. Newns
IPC分类号： H01L47/00
CPC分类号： H01L45/1683 , G11C13/0004 , G11C17/16 , G11C17/165 , H01L45/06 , H01L45/1206 , H01L45/122 , H01L45/126 , H01L45/144 , H01L45/148
摘要： A structure including a phase change material and a related method are disclosed. The structure may include a first electrode; a second electrode; a third electrode; a phase change material electrically connecting the first, second and third electrodes for passing a first current through two of the first, second and third electrodes; and a refractory metal barrier heater layer about the phase change material for converting the phase change material between an amorphous, insulative state and a crystalline, conductive state by application of a second current to the phase change material. The structure may be used as a fuse or a phase change material random access memory (PRAM).
摘要翻译： 公开了包括相变材料和相关方法的结构。 该结构可以包括第一电极; 第二电极; 第三电极; 相变材料，电连接第一，第二和第三电极，用于使第一电流通过第一，第二和第三电极中的两个; 以及围绕所述相变材料的难熔金属阻挡加热器层，用于通过向相变材料施加第二电流来在非晶态绝缘状态和结晶导电状态之间转换相变材料。 该结构可以用作保险丝或相变材料随机存取存储器（PRAM）。
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公开(公告)号：US07566593B2
公开(公告)日：2009-07-28
申请号：US11538170
申请日：2006-10-03
IPC分类号： H01L21/82
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure comprises a cavity interposed between a substrate and a fuse material layer. The cavity is not formed at a sidewall of the fuse material layer, or at a surface of the fuse material layer opposite the substrate. A void may be formed interposed between the substrate and the fuse material layer while using a self-aligned etching method, when the fuse material layer comprises lobed ends and a narrower middle region. The void is separated by a pair of sacrificial layer pedestals that support the fuse material layer. The void is encapsulated to form the cavity by using an encapsulating dielectric layer. Alternatively, a block mask may be used when forming the void interposed between the substrate and the fuse material layer.
摘要翻译： 熔丝结构包括插入在基板和熔丝材料层之间的空腔。 空腔不形成在熔丝材料层的侧壁处，或者在与衬底相对的熔丝材料层的表面处。 当熔丝材料层包括裂纹末端和较窄的中间区域时，可以在使用自对准蚀刻方法的同时在衬底和熔丝材料层之间形成空隙。 空隙由支撑熔丝材料层的一对牺牲层基座分开。 通过使用封装介电层将空隙封装以形成空腔。 或者，当形成插入在基板和熔丝材料层之间的空隙时，可以使用块掩模。
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公开(公告)号：US20090045388A1
公开(公告)日：2009-02-19
申请号：US11839724
申请日：2007-08-16
申请人： Lawrence A. Clevenger , Bruce G. Elmegreen , Deok-Kee Kim , Chandrasekharan Kothandaraman , Lia Krusin-Elbaum , Chung H. Lam , Dennis M. Newns
发明人： Lawrence A. Clevenger , Bruce G. Elmegreen , Deok-Kee Kim , Chandrasekharan Kothandaraman , Lia Krusin-Elbaum , Chung H. Lam , Dennis M. Newns
IPC分类号： H01L45/00
CPC分类号： H01L45/1683 , G11C13/0004 , G11C17/16 , G11C17/165 , H01L45/06 , H01L45/1206 , H01L45/122 , H01L45/126 , H01L45/144 , H01L45/148
摘要： A structure including a phase change material and a related method are disclosed. The structure may include a first electrode; a second electrode; a third electrode; a phase change material electrically connecting the first, second and third electrodes for passing a first current through two of the first, second and third electrodes; and a refractory metal barrier heater layer about the phase change material for converting the phase change material between an amorphous, insulative state and a crystalline, conductive state by application of a second current to the phase change material. The structure may be used as a fuse or a phase change material random access memory (PRAM).
摘要翻译： 公开了包括相变材料和相关方法的结构。 该结构可以包括第一电极; 第二电极; 第三电极; 相变材料，电连接第一，第二和第三电极，用于使第一电流通过第一，第二和第三电极中的两个; 以及围绕所述相变材料的难熔金属阻挡加热器层，用于通过向相变材料施加第二电流来在非晶态绝缘状态和结晶导电状态之间转换相变材料。 该结构可以用作保险丝或相变材料随机存取存储器（PRAM）。
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公开(公告)号：US20080217658A1
公开(公告)日：2008-09-11
申请号：US11683075
申请日：2007-03-07
CPC分类号： H01L27/112 , H01L23/5252 , H01L27/101 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The present invention provides structures for antifuses that utilize electromigration for programming. By providing a portion of antifuse link with high resistance without conducting material and then by inducing electromigration of the conducting material into the antifuse link, the resistance of the antifuse structure is changed. By providing a terminal on the antifuse link, the change in the electrical properties of the antifuse link is detected and sensed. Also disclosed are an integrated antifuse with a built-in sensing device and a two dimensional array of integrated antifuses that can share programming transistors and sensing circuitry.
摘要翻译： 本发明提供了利用电迁移进行编程的反熔丝的结构。 通过在没有导电材料的情况下提供具有高电阻的一部分反熔丝连接，然后通过将导电材料电迁移到反熔丝连接中，反熔丝结构的电阻改变。 通过在反熔丝链路上设置端子，检测和感测反熔丝连接的电特性的变化。 还公开了具有内置感测装置的集成反熔丝和可共享编程晶体管和感测电路的集成反熔丝的二维阵列。
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公开(公告)号：US08163640B2
公开(公告)日：2012-04-24
申请号：US11874385
申请日：2007-10-18
IPC分类号： H01L27/06 , H01L21/3205
CPC分类号： H01L27/0617 , H01L23/5256 , H01L29/4238 , H01L2924/0002 , H01L2924/00
摘要： A dielectric material layer is formed on a metal gate layer for a metal gate electrode, and then lithographically patterned to form a dielectric material portion, followed by formation of a polycrystalline semiconductor layer thereupon. A semiconductor device employing a metal gate electrode is formed in a region of the semiconductor substrate containing a vertically abutting stack of the metal gate layer and the polycrystalline semiconductor layer. A material stack in the shape of an electrical fuse is formed in another region of the semiconductor substrate containing a vertical stack of the metal gate layer, the dielectric material portion, and the polycrystalline semiconductor layer. After metallization of the polycrystalline semiconductor layer, an electrical fuse containing a polycrystalline semiconductor portion and a metal semiconductor alloy portion is formed over the dielectric material portion that separates the electrical fuse from the metal gate layer.
摘要翻译： 在用于金属栅电极的金属栅极层上形成电介质材料层，然后通过光刻图案形成电介质材料部分，随后在其上形成多晶半导体层。 在包含金属栅极层和多晶半导体层的垂直邻接堆叠的半导体基板的区域中形成采用金属栅电极的半导体器件。 形成有电熔丝形状的材料堆叠形成在半导体衬底的另一区域中，该区域包含金属栅极层，电介质材料部分和多晶半导体层的垂直叠层。 在多晶半导体层的金属化之后，在将电熔丝与金属栅极层分离开的电介质材料部分上形成包含多晶半导体部分和金属半导体合金部分的电熔丝。
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