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    eFuse containing SiGe stack
    6.
    发明授权
    eFuse containing SiGe stack 有权
    eFuse包含SiGe堆栈

    公开(公告)号：US08004059B2

    公开(公告)日：2011-08-23

    申请号：US11622616

    申请日：2007-01-12

    申请人： Deok-Kee Kim ,  Dureseti Chidambarrao ,  William K. Henson ,  Chandrasekharan Kothandaraman

    发明人： Deok-Kee Kim ,  Dureseti Chidambarrao ,  William K. Henson ,  Chandrasekharan Kothandaraman

    IPC分类号： H01L23/525

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.

    摘要翻译： eFuse包括：衬底和设置在衬底上的绝缘层; 包括设置在所述绝缘层上的单晶或多晶硅的第一层; 包括设置在第一层上的单晶或多晶硅锗的第二层，以及包括设置在第二层上的硅化物的第三层。 Ge的终浓度范围约为百分之五至百分之二十五。

    Fuse structure including cavity and methods for fabrication thereof
    8.
    发明授权
    Fuse structure including cavity and methods for fabrication thereof 失效
    保险丝结构，包括腔体及其制造方法

    公开(公告)号：US07566593B2

    公开(公告)日：2009-07-28

    申请号：US11538170

    申请日：2006-10-03

    申请人： Anil K. Chinthakindi ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman

    发明人： Anil K. Chinthakindi ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman

    IPC分类号： H01L21/82

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A fuse structure comprises a cavity interposed between a substrate and a fuse material layer. The cavity is not formed at a sidewall of the fuse material layer, or at a surface of the fuse material layer opposite the substrate. A void may be formed interposed between the substrate and the fuse material layer while using a self-aligned etching method, when the fuse material layer comprises lobed ends and a narrower middle region. The void is separated by a pair of sacrificial layer pedestals that support the fuse material layer. The void is encapsulated to form the cavity by using an encapsulating dielectric layer. Alternatively, a block mask may be used when forming the void interposed between the substrate and the fuse material layer.

    摘要翻译： 熔丝结构包括插入在基板和熔丝材料层之间的空腔。 空腔不形成在熔丝材料层的侧壁处，或者在与衬底相对的熔丝材料层的表面处。 当熔丝材料层包括裂纹末端和较窄的中间区域时，可以在使用自对准蚀刻方法的同时在衬底和熔丝材料层之间形成空隙。 空隙由支撑熔丝材料层的一对牺牲层基座分开。 通过使用封装介电层将空隙封装以形成空腔。 或者，当形成插入在基板和熔丝材料层之间的空隙时，可以使用块掩模。

    ELECTRICAL ANTIFUSE WITH INTEGRATED SENSOR
    9.
    发明申请
    ELECTRICAL ANTIFUSE WITH INTEGRATED SENSOR 有权
    集成传感器的电气防护

    公开(公告)号：US20080217658A1

    公开(公告)日：2008-09-11

    申请号：US11683075

    申请日：2007-03-07

    申请人： Deok-kee Kim ,  Hoki Kim ,  Chandrasekharan Kothandaraman ,  Byeongju Park ,  John M. Safran

    发明人： Deok-kee Kim ,  Hoki Kim ,  Chandrasekharan Kothandaraman ,  Byeongju Park ,  John M. Safran

    IPC分类号： H01L27/10 ,  H01L29/00

    CPC分类号： H01L27/112 ,  H01L23/5252 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： The present invention provides structures for antifuses that utilize electromigration for programming. By providing a portion of antifuse link with high resistance without conducting material and then by inducing electromigration of the conducting material into the antifuse link, the resistance of the antifuse structure is changed. By providing a terminal on the antifuse link, the change in the electrical properties of the antifuse link is detected and sensed. Also disclosed are an integrated antifuse with a built-in sensing device and a two dimensional array of integrated antifuses that can share programming transistors and sensing circuitry.

    摘要翻译： 本发明提供了利用电迁移进行编程的反熔丝的结构。 通过在没有导电材料的情况下提供具有高电阻的一部分反熔丝连接，然后通过将导电材料电迁移到反熔丝连接中，反熔丝结构的电阻改变。 通过在反熔丝链路上设置端子，检测和感测反熔丝连接的电特性的变化。 还公开了具有内置感测装置的集成反熔丝和可共享编程晶体管和感测电路的集成反熔丝的二维阵列。

    Metal gate compatible electrical fuse
    10.
    发明授权
    Metal gate compatible electrical fuse 失效
    金属门兼容电保险丝

    公开(公告)号：US08163640B2

    公开(公告)日：2012-04-24

    申请号：US11874385

    申请日：2007-10-18

    申请人： Xiangdong Chen ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman

    发明人： Xiangdong Chen ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman

    IPC分类号： H01L27/06 ,  H01L21/3205

    CPC分类号： H01L27/0617 ,  H01L23/5256 ,  H01L29/4238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A dielectric material layer is formed on a metal gate layer for a metal gate electrode, and then lithographically patterned to form a dielectric material portion, followed by formation of a polycrystalline semiconductor layer thereupon. A semiconductor device employing a metal gate electrode is formed in a region of the semiconductor substrate containing a vertically abutting stack of the metal gate layer and the polycrystalline semiconductor layer. A material stack in the shape of an electrical fuse is formed in another region of the semiconductor substrate containing a vertical stack of the metal gate layer, the dielectric material portion, and the polycrystalline semiconductor layer. After metallization of the polycrystalline semiconductor layer, an electrical fuse containing a polycrystalline semiconductor portion and a metal semiconductor alloy portion is formed over the dielectric material portion that separates the electrical fuse from the metal gate layer.

    摘要翻译： 在用于金属栅电极的金属栅极层上形成电介质材料层，然后通过光刻图案形成电介质材料部分，随后在其上形成多晶半导体层。 在包含金属栅极层和多晶半导体层的垂直邻接堆叠的半导体基板的区域中形成采用金属栅电极的半导体器件。 形成有电熔丝形状的材料堆叠形成在半导体衬底的另一区域中，该区域包含金属栅极层，电介质材料部分和多晶半导体层的垂直叠层。 在多晶半导体层的金属化之后，在将电熔丝与金属栅极层分离开的电介质材料部分上形成包含多晶半导体部分和金属半导体合金部分的电熔丝。