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公开(公告)号：US20120147661A1
公开(公告)日：2012-06-14
申请号：US12963965
申请日：2010-12-09
IPC分类号： G11C11/4072
CPC分类号： G11C11/4072
摘要： A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by driving the wordlines of all the cells to an activated state. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value. In a preferred embodiment, the wordlines are all turned on simultaneously during a power on reset period. Preferably a power on reset signal is used to drive each logic gate of the pre-decoder portion of the address decoder in order to assert all the wordlines.
摘要翻译： 电路和方法在上电时擦除存储在DRAM芯片中的所有数据，以提高数据安全性。 通过将所有单元的字线驱动到激活状态，同时通过接通DRAM存储单元的晶体管来擦除所有的DRAM存储单元。 当所有设备都打开时，存储在存储单元中的数据将被擦除，因为连接到通用位线的所有单元的电压合并为单个值。 在优选实施例中，在上电复位周期期间，字线都同时导通。 优选地，上电复位信号用于驱动地址解码器的预解码器部分的每个逻辑门，以便断言所有字线。
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公开(公告)号：US20130235681A1
公开(公告)日：2013-09-12
申请号：US13414133
申请日：2012-03-07
申请人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Michael Launsbach , Daniel M. Nelson
发明人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Michael Launsbach , Daniel M. Nelson
CPC分类号： G11C7/12 , G11C11/419
摘要： A method and circuit for implementing delay correction in static random access memory (SRAM), and a design structure on which the subject circuit resides are provided. The SRAM circuit includes a precharge enable signal coupled between precharge near and precharge far signals and wordline near and wordline far signals of the SRAM. A precharge pull down device is coupled between the precharge far signal and ground and is controlled responsive to the precharge enable signal to decrease a time delay of the falling transition of the precharge far signal. A respective word line pull up device is coupled between a respective wordline far signal and a voltage supply rail and is controlled responsive to the precharge enable signal to increase wordline voltage level upon a rising transition of the wordline far signal.
摘要翻译： 一种用于实现静态随机存取存储器（SRAM）中的延迟校正的方法和电路，以及设置有被摄体电路所在的设计结构。 SRAM电路包括预充电接近和预充电远信号以及SRAM的字线附近和字线远信号之间的预充电使能信号。 预充电下拉装置耦合在预充电远信号和地之间，并且响应于预充电使能信号被控制以减小预充电远信号的下降转换的时间延迟。 相应的字线上拉器件耦合在相应的字线远信号和电压供应轨之间，并且响应于预充电使能信号被控制，以在字线远信号的上升转变时增加字线电压电平。
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公开(公告)号：US08520429B2
公开(公告)日：2013-08-27
申请号：US13101436
申请日：2011-05-05
申请人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Michael Launsbach , Daniel M. Nelson
发明人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Michael Launsbach , Daniel M. Nelson
CPC分类号： G11C11/413
摘要： A semiconductor chip has an SRAM (static random access memory). The SRAM includes a data dependent write assist circuit which, on writes, reduces a supply voltage on one of a cross coupled inverter pair in an SRAM cell, thereby making it easier to overcome the one of the cross coupled inverters.
摘要翻译： 半导体芯片具有SRAM（静态随机存取存储器）。 SRAM包括数据相关写入辅助电路，其在写入时降低SRAM单元中的交叉耦合的反相器对中的一个上的电源电压，从而使得更容易克服交叉耦合的反相器之一。
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公开(公告)号：US20090309644A1
公开(公告)日：2009-12-17
申请号：US12138564
申请日：2008-06-13
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K2005/00026 , H03K2005/0013
摘要： The present disclosure is an apparatus for generating a decreasing delay with increasing input voltage to a predetermined voltage value at which point the delay may remain constant. The apparatus may include a circuit comprising a voltage regulator receiving an input voltage and two paths of inverters. At least two paths of inverters may be coupled to an input signal, the input signal may be low voltage (e.g. 0) or high voltage (e.g. 1). A first path may be referenced to a reference voltage while the second path may be referenced to the input voltage. The apparatus may include logic gates for receiving the output of each of the first path of inverters and the output of the second path of inverters to generate a desired output. As the input voltage increases, delay of the apparatus may decrease until the input voltage is approximately the same voltage as the reference voltage, at which the delay may remain constant.
摘要翻译： 本公开是一种用于通过将输入电压增加到预定电压值来产生递减延迟的装置，在该点处延迟可以保持恒定。 该装置可以包括电路，该电路包括接收输入电压的电压调节器和两个逆变器路径。 反相器的至少两个路径可以耦合到输入信号，输入信号可以是低电压（例如0）或高电压（例如1）。 第一路径可以参考参考电压，而第二路径可以参考输入电压。 该装置可以包括逻辑门，用于接收每个逆变器的第一路径的输出和第二路径的反相器的输出以产生期望的输出。 当输入电压增加时，装置的延迟可能减小，直到输入电压与参考电压大致相同的电压，在该电压处延迟可以保持恒定。
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15.发明授权Implementing single bit redundancy for dynamic SRAM circuit with any bit decode 失效用任意位解码实现动态SRAM电路的单位冗余公开(公告)号：US08427894B2
公开(公告)日：2013-04-23
申请号：US12886692
申请日：2010-09-21
申请人： Derick G. Behrends , Todd A. Christensen , Peter T. Freiburger , Travis R. Hebig , Jayson K. Wittrup
发明人： Derick G. Behrends , Todd A. Christensen , Peter T. Freiburger , Travis R. Hebig , Jayson K. Wittrup
CPC分类号： G11C29/846
摘要： A method and a dynamic Static Random Access Memory (SRAM) circuit for implementing single bit redundancy with any bit decode, and a design structure on which the subject circuit resides are provided. The SRAM circuit includes a plurality of bitline columns and a pair of redundancy columns respectively coupled to a respective merged bit column select and redundancy steering multiplexer. Each merged bit column select and redundancy steering multiplexer receives a respective select signal input. A select signal generation circuit receives a redundancy steering signal and a respective one-hot bit select signal, generating the respective select signal input.
摘要翻译： 一种用于实现具有任何位解码的单位冗余的方法和动态静态随机存取存储器（SRAM）电路，以及提供主题电路所在的设计结构。 SRAM电路包括分别耦合到相应的合并位列选择和冗余转向多路复用器的多个位线列和一对冗余列。 每个合并位列选择和冗余转向多路复用器接收相应的选择信号输入。 选择信号发生电路接收冗余转向信号和相应的一个热位选择信号，产生相应的选择信号输入。
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公开(公告)号：US08578304B1
公开(公告)日：2013-11-05
申请号：US13558468
申请日：2012-07-26
IPC分类号： G06F17/50
CPC分类号： G03F1/70
摘要： A method, system and computer program product are provided for implementing multiple mask lithography timing variation mitigation for a multiple mask polysilicon (PC) process. An application specific integrated circuit (ASIC) library includes at least one circuit device for a first mask, and at least one circuit device for a second mask. Critical hold time paths and critical setup time paths are identified in a circuit design. For critical hold time paths, circuit devices in the critical hold time paths are placed on a single mask of either the first mask or the second mask. For critical setup time paths, path delays are reduced by providing a mixture of circuit devices on the first mask and the second mask.
摘要翻译： 提供了一种方法，系统和计算机程序产品，用于实现多掩模多晶硅（PC）处理的多掩模光刻定时变化减轻。 专用集成电路（ASIC）库包括用于第一掩模的至少一个电路装置和用于第二掩模的至少一个电路装置。 在电路设计中标识临界保持时间路径和关键建立时间路径。 对于临界保持时间路径，临界保持时间路径中的电路设备放置在第一掩模或第二掩模的单个掩模上。 对于关键的建立时间路径，通过在第一掩模和第二掩模上提供电路装置的混合来减少路径延迟。
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公开(公告)号：US08108739B2
公开(公告)日：2012-01-31
申请号：US12110955
申请日：2008-04-28
CPC分类号： G11C29/48 , G11C11/41 , G11C29/12 , G11C29/1201 , G11C29/50012 , G11C2029/0401
摘要： A method for allowing high-speed testability of a memory device having a core with memory cells for storing data, comprising: enabling a data signal having a first logical state or a second logical state from the core to reach an output port of the memory device within an evaluate cycle during a functional operating mode and pass an array built in self test during LBIST mode; enabling the data signal to change from the first logical state to the second logical state during LBIST mode at a time that coincides with the latest possible time the data signal from the core can reach the read output port within the evaluate cycle during the functional operating mode and pass the array built in self test; and executing a logic built-in self test configured to test a logic block located downstream of a transmission path of the memory device.
摘要翻译： 一种用于允许具有用于存储数据的存储器单元的具有核的存储器件的高速可测试性的方法，包括：使得具有来自所述核的第一逻辑状态或第二逻辑状态的数据信号到达所述存储器件的输出端口 在功能操作模式的评估周期内，并且在LBIST模式期间通过内置自检的阵列; 使得数据信号在LBIST模式期间能够在LBIST模式期间从与核心的数据信号在功能操作模式期间到达评估周期内的读取输出端口的最新可能时间一致的时刻改变为第一逻辑状态 并通过自检内置的数组; 以及执行被配置为测试位于所述存储器件的传输路径下游的逻辑块的逻辑内置自检。
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公开(公告)号：US20130222031A1
公开(公告)日：2013-08-29
申请号：US13404096
申请日：2012-02-24
IPC分类号： H03K3/289
CPC分类号： H03K3/012 , H03K3/0375
摘要： A method and circuits for implementing power saving self powering down latch operation, and a design structure on which the subject circuit resides are provided. A master slave latch includes a virtual power supply connection. At least one connection control device is coupled between the virtual power supply connection and a voltage supply rail. A driver gate applies a power down signal driving the at least one connection control device to control the at least one connection control device during a self power down mode. The driver gate combines a self power down input signal and a latch data output signal to generate the power down signal.
摘要翻译： 一种用于实现省电自掉电锁存器操作的方法和电路，以及设置有该电路所在的设计结构。 主从锁存器包括虚拟电源连接。 至少一个连接控制装置耦合在虚拟电源连接和电压供应导轨之间。 驱动器门施加驱动所述至少一个连接控制装置的掉电信号，以在自省电模式期间控制所述至少一个连接控制装置。 驱动器门组合自省电输入信号和锁存数据输出信号以产生掉电信号。
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公开(公告)号：US20090271669A1
公开(公告)日：2009-10-29
申请号：US12110955
申请日：2008-04-28
CPC分类号： G11C29/48 , G11C11/41 , G11C29/12 , G11C29/1201 , G11C29/50012 , G11C2029/0401
摘要： A method for allowing high-speed testability of a memory device having a core with memory cells for storing data, comprising: enabling a data signal having a first logical state or a second logical state from the core to reach an output port of the memory device within an evaluate cycle during a functional operating mode and pass an array built in self test during LBIST mode; enabling the data signal to change from the first logical state to the second logical state during LBIST mode at a time that coincides with the latest possible time the data signal from the core can reach the read output port within the evaluate cycle during the functional operating mode and pass the array built in self test; and executing a logic built-in self test configured to test a logic block located downstream of a transmission path of the memory device.
摘要翻译： 一种用于允许具有用于存储数据的存储器单元的具有核的存储器件的高速可测试性的方法，包括：使得具有来自所述核的第一逻辑状态或第二逻辑状态的数据信号到达所述存储器件的输出端口 在功能操作模式的评估周期内，并且在LBIST模式期间通过内置自检的阵列; 使得数据信号在LBIST模式期间能够在LBIST模式期间从与核心的数据信号在功能操作模式期间到达评估周期内的读取输出端口的最新可能时间一致的时刻改变为第一逻辑状态 并通过自检内置的数组; 以及执行被配置为测试位于所述存储器件的传输路径下游的逻辑块的逻辑内置自检。
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公开(公告)号：US08669800B2
公开(公告)日：2014-03-11
申请号：US13404096
申请日：2012-02-24
IPC分类号： H03K3/289
CPC分类号： H03K3/012 , H03K3/0375
摘要： A method and circuits for implementing power saving self powering down latch operation, and a design structure on which the subject circuit resides are provided. A master slave latch includes a virtual power supply connection. At least one connection control device is coupled between the virtual power supply connection and a voltage supply rail. A driver gate applies a power down signal driving the at least one connection control device to control the at least one connection control device during a self power down mode. The driver gate combines a self power down input signal and a latch data output signal to generate the power down signal.
摘要翻译： 一种用于实现省电自掉电锁存器操作的方法和电路，以及设置有该电路所在的设计结构。 主从锁存器包括虚拟电源连接。 至少一个连接控制装置耦合在虚拟电源连接和电压供应导轨之间。 驱动器门施加驱动所述至少一个连接控制装置的掉电信号，以在自省电模式期间控制所述至少一个连接控制装置。 驱动器门组合自省电输入信号和锁存数据输出信号以产生掉电信号。
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