-
公开(公告)号：US20060092589A1
公开(公告)日：2006-05-04
申请号：US10977881
申请日：2004-10-29
IPC分类号： H02H9/00
CPC分类号： H01L27/0266
摘要： An ESD protection circuit for protecting a circuit from an ESD event occurring between a first voltage supply node and a second voltage supply node associated with the circuit to be protected includes an MOS device having a gate terminal, a first source/drain terminal and a second source/drain terminal. The first source/drain terminal is connected to the first voltage supply node and the second source/drain terminal is connected to the second voltage supply node. The ESD protection circuit further includes a trigger circuit coupled to the gate terminal of the MOS device. The trigger circuit is configured to generate a control signal at the gate terminal of the MOS device for activating the MOS device during the ESD event. At least a portion of the trigger circuit is formed in a floating well which becomes biased to a voltage that is substantially equal to a first voltage when the first voltage is supplied to the first voltage supply node or to a second voltage when the second voltage is applied to the second voltage supply node, whichever voltage is greater.
-
公开(公告)号：US20060066381A1
公开(公告)日：2006-03-30
申请号：US10956000
申请日：2004-09-30
申请人： Dipankar Bhattacharya , John Kriz , Brian Lacey , Bruce McNeill , Bernard Morris
发明人： Dipankar Bhattacharya , John Kriz , Brian Lacey , Bruce McNeill , Bernard Morris
IPC分类号： H03L5/00
CPC分类号： H03K3/356113 , H03K3/356008 , H03K17/223
摘要： A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal and a latch circuit for storing a signal at an output of the latch circuit which is representative of a logical state of the input signal. The latch circuit includes an input coupled to the input stage. The voltage level translator circuit further includes a feedback circuit coupled between the input and the output of the latch circuit. The feedback circuit is operative to maintain a desired logic state of the voltage level translator circuit when the second voltage supply powers up before the first voltage supply. In this manner, the voltage level translator circuit is configured to provide an output signal having a predictable logic state over a wide variation of PVT conditions and/or voltage supply ramp rates.
摘要翻译： 用于将参考第一电压源的输入信号转换为参考第二电压源的输出信号的电压电平转换器电路包括用于接收输入信号的输入级和用于在锁存电路的输出端存储信号的锁存电路 其代表输入信号的逻辑状态。 锁存电路包括耦合到输入级的输入端。 电压电平转换器电路还包括耦合在锁存电路的输入和输出之间的反馈电路。 当第二电压源在第一电压供应之前加电时，反馈电路可操作以保持电压电平转换器电路的期望逻辑状态。 以这种方式，电压电平转换器电路被配置为在PVT条件和/或电压提供斜坡率的宽泛变化上提供具有可预测逻辑状态的输出信号。
-
13.发明申请公开(公告)号：US20060044028A1
公开(公告)日：2006-03-02
申请号：US10925613
申请日：2004-08-25
IPC分类号： H03L7/00
CPC分类号： H03K17/223
摘要： A PUR circuit for generating a reset signal includes a first node for receiving a reference voltage and a second node for receiving a supply voltage that is referenced with respect to the reference voltage. The circuit further includes a voltage level detector coupled between the first node and a third node, the voltage level detector being configured to generate a first control signal at the third node. The voltage level detector includes a first transistor having a first threshold voltage associated therewith. A resistance element is coupled between the second node and the third node, the resistance element having a first resistance value associated therewith. The circuit also includes an inverter having an input coupled to the third node and having an output for generating a second control signal in response to the first control signal. The inverter includes a second transistor having a second threshold voltage associated therewith which is lower than the first threshold voltage. The voltage level detector is configured such that the first control signal is substantially equal to the supply voltage when the supply voltage is less than a first voltage, and the first control signal is equal to a second voltage when the supply voltage is substantially equal to or greater than the first voltage. The second voltage is less than a lower switching point of the inverter, the first voltage being based at least in part on the first threshold voltage, the reset signal being a function of the second control signal.
摘要翻译： 用于产生复位信号的PUR电路包括用于接收参考电压的第一节点和用于接收相对于参考电压参考的电源电压的第二节点。 电路还包括耦合在第一节点和第三节点之间的电压电平检测器，电压电平检测器被配置为在第三节点处产生第一控制信号。 电压电平检测器包括具有与其相关联的第一阈值电压的第一晶体管。 电阻元件耦合在第二节点和第三节点之间，电阻元件具有与之相关联的第一电阻值。 该电路还包括具有耦合到第三节点并具有响应于第一控制信号产生第二控制信号的输出的反相器。 逆变器包括具有与其相关联的第二阈值电压的第二晶体管，其低于第一阈值电压。 电压电平检测器被配置为使得当电源电压小于第一电压时，第一控制信号基本上等于电源电压，并且当电源电压基本上等于或等于第一控制信号时，第一控制信号等于第二电压 大于第一电压。 第二电压小于逆变器的较低开关点，第一电压至少部分地基于第一阈值电压，复位信号是第二控制信号的函数。
-
公开(公告)号：US06992489B2
公开(公告)日：2006-01-31
申请号：US10776778
申请日：2004-02-11
IPC分类号： G01R19/26 , G01R19/257
CPC分类号： G01R19/16595 , G01R19/16519
摘要： A circuit configurable for indicating a voltage level of an input signal applied to the circuit includes at least one transistor having a first terminal connected to a first voltage supply, a second terminal configured for receiving the input signal, and a third terminal operatively coupled to an output of the circuit. The circuit further includes a passive load connected between the third terminal of the transistor and a second voltage supply. The circuit is configured to generate an output signal at the output of the circuit. The output signal being at a first value indicates that the input signal is substantially at a first voltage level, and the output signal being at a second value indicates that the input signal is substantially at a second voltage level.
摘要翻译： 可配置为指示施加到电路的输入信号的电压电平的电路包括至少一个晶体管，其具有连接到第一电压源的第一端子，被配置为接收输入信号的第二端子，以及可操作地耦合到 输出电路。 电路还包括连接在晶体管的第三端子和第二电压源之间的无源负载。 电路被配置为在电路的输出处产生输出信号。 输出信号处于第一值表示输入信号基本上处于第一电压电平，并且输出信号处于第二值表示输入信号基本上处于第二电压电平。
-
公开(公告)号：US20050270065A1
公开(公告)日：2005-12-08
申请号：US10859211
申请日：2004-06-03
IPC分类号： H03K3/00 , H03K17/0412 , H03K17/06 , H03K19/0175 , H03K19/0185
CPC分类号： H03K19/018585 , H03K17/04123 , H03K17/063 , H03K19/018521
摘要： A buffer design for an integrated circuit that not only recognizes, but improves upon the skew problem as described above that is particularly problematic in cases where the output buffer supply voltage is particularly close or the same as the voltage of the signals coming from the core of an IC. Translator-up circuits associated with output buffers are implemented in parallel with respective selective bypass circuits, allowing the translator-up circuit to be inserted into or removed from a signal path based on the voltage level of a signal received from the inner core and the voltage level required by the output buffer. When the voltage level of the “higher” voltage side is equal to the “lower” voltage signal level, the translator-up circuits are bypassed through selection by a selective bypass circuit. Thus, a selective bypass circuit is implemented together with a translator-up circuit to eliminate large signal skew, and to generally speed up circuit performance.
摘要翻译： 一种用于集成电路的缓冲器设计，其不仅识别但改进了如上所述的偏斜问题，在输出缓冲器电源电压特别接近或相同于来自芯的信号的电压的情况下，这是特别有问题的 一个IC 与输出缓冲器相关联的转换电路与相应的选择旁路电路并行实现，允许转换器升高电路基于从内核接收的信号的电压电平和电压插入或从信号路径中去除 输出缓冲区所需的电平。 当“较高”电压侧的电压电平等于“较低”电压信号电平时，通过选择旁路电路的选择旁路转换器电路。 因此，选择性旁路电路与转换器升压电路一起实现，以消除大的信号偏移，并且通常加速电路性能。
-
公开(公告)号：US08089739B2
公开(公告)日：2012-01-03
申请号：US12438460
申请日：2007-10-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
CPC分类号： H01L27/0266
摘要： An ESD protection circuit includes a first voltage clamp, connected between a first voltage supply node and a second voltage supply node of the circuit, and a second voltage clamp, connected between the second voltage supply node and a voltage return of the circuit. The first voltage supply node is adapted to receive a first voltage which is greater than a prescribed gate oxide reliability potential of the circuit. The second voltage supply node is operative to receive a second voltage which is less than the first voltage. The first voltage clamp is operative to clamp the first voltage on the first voltage supply node to a first value during an ESD event between the first and second voltage supply nodes, and the second voltage clamp is operative to clamp the second voltage on the second voltage supply node to a second value during an ESD event between the second voltage supply node and the voltage return.
摘要翻译： ESD保护电路包括连接在电路的第一电压供应节点和第二电压供应节点之间的第一电压钳位器，以及连接在第二电压供应节点和电路的电压回路之间的第二电压钳位。 第一电压供应节点适于接收大于电路的预定栅极氧化物可靠性电位的第一电压。 第二电压供应节点可操作以接收小于第一电压的第二电压。 第一电压钳位器用于在第一和第二电压供应节点之间的ESD事件期间将第一电压供应节点上的第一电压钳位到第一值，并且第二电压钳位器用于将第二电压钳位在第二电压 在第二电压供应节点和电压返回之间的ESD事件期间将供应节点提供给第二值。
-
公开(公告)号：US07720107B2
公开(公告)日：2010-05-18
申请号：US10989703
申请日：2004-11-15
CPC分类号： G06F13/4291 , H04J3/0632 , H04L7/0008 , H04L7/041 , H04L25/14
摘要： A source-synchronous parallel interface divides a wide data bus into clock-groups including a sub-group of the data lines and a clock line carrying a copy of the transmit clock. The traces in a clock-group are located physically close together to minimize skew between the signals carried on the traces of the clock-group. Deskew logic on the receiver compensates for skew between received clock-group signals.
摘要翻译： 源同步并行接口将宽数据总线分为时钟组，包括数据线的子组和携带传输时钟副本的时钟线。 时钟组中的迹线物理上靠近在一起，以最小化时钟组迹线上携带的信号之间的偏移。 接收机上的偏移校正逻辑补偿接收的时钟组信号之间的偏差。
-
公开(公告)号：US07432762B2
公开(公告)日：2008-10-07
申请号：US11393171
申请日：2006-03-30
CPC分类号： H03F3/45183 , H03F2200/513 , H03F2200/78 , H03F2203/45314 , H03F2203/45361 , H03F2203/45552 , H03F2203/45684
摘要： A circuit having an enhanced input signal range includes a differential amplifier operative to receive at least first and second signals and to generate a difference signal at an output thereof which is a function of the difference between the first and second signals. The differential amplifier includes an input stage having at least first and second transistors having a first threshold voltage associated therewith and being operative to receive the first and second signals, respectively, and a load including at least third and fourth transistors having a second threshold voltage associated therewith, the first threshold voltage being greater than the second threshold voltage. The circuit further includes an output stage coupled to the differential amplifier and operative to receive the difference signal and to generate an output signal of the circuit that is indicative of the difference signal and is referenced to the supply voltage of the circuit.
摘要翻译： 具有增强的输入信号范围的电路包括差分放大器，其操作以接收至少第一和第二信号，并在其输出处产生作为第一和第二信号之间的差的函数的差分信号。 差分放大器包括具有至少第一和第二晶体管的输入级，其具有与其相关联的第一阈值电压，并且可分别接收第一和第二信号，并且负载包括至少第三和第四晶体管，其具有第二阈值电压相关联 因此，第一阈值电压大于第二阈值电压。 电路还包括耦合到差分放大器的输出级并且可操作地接收差分信号并产生指示差分信号的电路的输出信号并且参考电路的电源电压。
-
公开(公告)号：US20080238399A1
公开(公告)日：2008-10-02
申请号：US11691590
申请日：2007-03-27
申请人： Dipankar Bhattacharya , Carol A. Huber , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
发明人： Dipankar Bhattacharya , Carol A. Huber , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
IPC分类号： G05F5/00
CPC分类号： H03K19/017581 , H03K19/01759
摘要： A buffer circuit is selectively operative in one of at least a first mode and a second mode as a function of a first control signal supplied to the buffer circuit. The buffer circuit includes interface circuitry operative to receive at least second and third control signals referenced to a first voltage level, and to generate an output signal referenced to a second voltage level, the second voltage level being greater than the first voltage level. The output signal is a function of the second control signal in the first mode and is a function of the third control signal in the second mode. The buffer circuit further includes at least first and second circuit portions coupled to the interface circuitry, each of the first and second circuit portions including at least one control input operative to receive the output signal generated by the interface circuitry.
摘要翻译： 作为提供给缓冲电路的第一控制信号的函数，缓冲器电路有选择地以至少第一模式和第二模式中的至少一个工作。 缓冲电路包括接口电路，其操作以接收参考第一电压电平的至少第二和第三控制信号，并产生参考第二电压电平的输出信号，第二电压电平大于第一电压电平。 输出信号是第一模式中的第二控制信号的函数，并且是第二模式中的第三控制信号的函数。 缓冲电路还包括耦合到接口电路的至少第一和第二电路部分，第一和第二电路部分中的每一个包括至少一个控制输入，其操作以接收由接口电路产生的输出信号。
-
公开(公告)号：US07430100B2
公开(公告)日：2008-09-30
申请号：US11169139
申请日：2005-06-28
IPC分类号： H02H3/20
CPC分类号： H03K19/00315 , H03K2217/0018
摘要： A buffer circuit having enhanced overvoltage protection includes core buffer circuitry couplable to a first voltage source having a first voltage level. The core buffer circuitry is configured to receive a first signal and to generate a second signal which is a function of the first signal. The buffer circuit further includes a protection circuit coupled between the core buffer circuitry and a signal pad. The protection circuit is operative: (i) to clamp the first signal to about the first voltage level when a third signal received at the signal pad exceeds the first voltage level by a first amount; and (ii) to generate the first signal being substantially equal to the third signal when the third signal is less than or substantially equal to the first voltage level.
摘要翻译： 具有增强的过电压保护的缓冲电路包括可耦合到具有第一电压电平的第一电压源的核心缓冲电路。 核心缓冲器电路被配置为接收第一信号并产生作为第一信号的函数的第二信号。 缓冲电路还包括耦合在核心缓冲器电路和信号焊盘之间的保护电路。 保护电路是可操作的：（i）当在信号焊盘处接收的第三信号超过第一电压电平达到第一量值时，将第一信号钳位到约第一电压电平; 和（ii）当第三信号小于或基本上等于第一电压电平时，产生基本上等于第三信号的第一信号。
-
-
-
-
-
-
-
-
-
搜索结果
80 条记录 (耗时 0.026 秒)