公开(公告)号：US08129770B2

公开(公告)日：2012-03-06

申请号：US12687001

申请日：2010-01-13

申请人： Shigeru Shiratake

发明人： Shigeru Shiratake

IPC分类号： H01L27/108 ,  H01L29/76

CPC分类号： H01L27/10855 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10888 ,  H01L27/10894

摘要： A semiconductor device includes a silicon substrate having an active region, a memory transistor having a pair of source/drain regions and a gate electrode layer, a hard mask layer on the gate electrode layer having a plane pattern shape identical with that of the gate electrode layer, and plug conductive layers each electrically connected to each of the pair of source/drain regions. An extending direction of the active region is not perpendicular to that of the gate electrode layer, but is oblique. Upper surfaces of the hard mask layer and each of the plug conductive layers form substantially an identical plane. This can attain a semiconductor device allowing significant enlargement of a margin in a photolithographic process, suppression of an “aperture defect” as well as ensuring of a process tolerance of a “short” by decreasing a microloading effect, and decrease in a contact resistance, and a manufacturing method thereof.

摘要翻译： 半导体器件包括具有有源区的硅衬底，具有一对源极/漏极区和栅极电极层的存储晶体管，栅电极层上的硬掩模层具有与栅电极的平面图形相同的平面图形 层，并且插塞导电层，每个导电层电连接到该对源/漏区中的每一个。 有源区的延伸方向不与栅电极层的延伸方向垂直，而是倾斜。 硬掩模层和每个插塞导电层的上表面基本上形成相同的平面。 这可以获得允许在光刻工艺中显着增大余量的半导体器件，抑制“孔径缺陷”以及通过减小微负载效应来确保“短路”的工艺公差，以及降低接触电阻， 及其制造方法。

公开(公告)号：US07935595B2

公开(公告)日：2011-05-03

申请号：US11581346

申请日：2006-10-17

申请人： Shigeru Shiratake

发明人： Shigeru Shiratake

IPC分类号： H01L21/00

CPC分类号： H01L27/10897 ,  H01L27/10876 ,  H01L27/10894

摘要： A method for manufacturing a semiconductor device whereby the process is simplified and high performance can be obtained in both a trench-gate transistor and a planar transistor that has a thin gate insulating film when the two transistors are formed on the same semiconductor substrate. In a state in which the gate insulating film (11s) in a peripheral circuit region PE is covered by a protective film (12), a gate trench (18) is formed in a memory cell region M, after which a gate insulating film (19) that is thicker than the gate insulating film (11s) is formed on an inner wall of the gate trench (18) in a state in which the gate insulating film (11s) of the peripheral circuit region PE is still covered by the protective film (12).

摘要翻译： 一种制造半导体器件的方法，其中当两个晶体管形成在同一半导体衬底上时，在沟槽栅极晶体管和具有薄栅绝缘膜的平面晶体管中，简化了工艺并获得了高性能。 在外围电路区域PE中的栅极绝缘膜（11s）被保护膜（12）覆盖的状态下，在存储单元区域M中形成栅极沟槽（18），然后将栅极绝缘膜（ 在外围电路区域PE的栅极绝缘膜（11s）仍然被保护层覆盖的状态下，在栅极沟槽（18）的内壁上形成比栅极绝缘膜（11s）厚的厚度 电影（12）。

公开(公告)号：US07705392B2

公开(公告)日：2010-04-27

申请号：US11402972

申请日：2006-04-13

申请人： Yasuaki Yonemochi ,  Hisakazu Otoi ,  Akio Nishida ,  Shigeru Shiratake

发明人： Yasuaki Yonemochi ,  Hisakazu Otoi ,  Akio Nishida ,  Shigeru Shiratake

IPC分类号： H01L29/76

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/7682 ,  H01L27/115 ,  H01L29/42324

摘要： A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.

摘要翻译： 一种具有主表面的半导体衬底，在半导体衬底的主表面上彼此隔开形成的第一和第二浮置栅极，分别位于第一和第二浮置栅极上的第一和第二控制栅极，形成在第一和第二浮置栅极上的第一绝缘膜 第一控制栅极，形成在第二控制栅极上以与第一绝缘膜接触的第二绝缘膜，以及通过实现第一绝缘膜和第二绝缘体之间的接触而形成在至少在第一浮栅和第二浮栅之间的间隙部分 包括电影。 由此，可以确保非易失性半导体器件的功能，并且可以抑制浮动栅极的阈值电压的变化。

公开(公告)号：US07674673B2

公开(公告)日：2010-03-09

申请号：US12018864

申请日：2008-01-24

申请人： Shigeru Shiratake

发明人： Shigeru Shiratake

IPC分类号： H01L27/148 ,  H01L29/768

CPC分类号： H01L27/10855 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10888 ,  H01L27/10894

摘要： A semiconductor device includes a silicon substrate having an active region, a memory transistor having a pair of source/drain regions and a gate electrode layer, a hard mask layer on the gate electrode layer having a plane pattern shape identical with that of the gate electrode layer, and plug conductive layers each electrically connected to each of the pair of source/drain regions. An extending direction of the active region is not perpendicular to that of the gate electrode layer, but is oblique. Upper surfaces of the hard mask layer and each of the plug conductive layers form substantially an identical plane. This can attain a semiconductor device allowing significant enlargement of a margin in a photolithographic process, suppression of an “aperture defect” as well as ensuring of a process tolerance of a “short” by decreasing a microloading effect, and decrease in a contact resistance, and a manufacturing method thereof.

摘要翻译： 半导体器件包括具有有源区的硅衬底，具有一对源极/漏极区和栅极电极层的存储晶体管，栅电极层上的硬掩模层具有与栅电极的平面图形相同的平面图形 层，并且插塞导电层，每个导电层电连接到该对源/漏区中的每一个。 有源区的延伸方向不与栅电极层的延伸方向垂直，而是倾斜。 硬掩模层和每个插塞导电层的上表面基本上形成相同的平面。 这可以获得允许在光刻工艺中显着增大余量的半导体器件，抑制“孔径缺陷”以及通过减小微负载效应来确保“短”的工艺公差，并且降低接触电阻， 及其制造方法。

公开(公告)号：US07339221B2

公开(公告)日：2008-03-04

申请号：US10961210

申请日：2004-10-12

申请人： Shigeru Shiratake

发明人： Shigeru Shiratake

IPC分类号： H01L27/108 ,  H01L29/76

CPC分类号： H01L27/10855 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10888 ,  H01L27/10894

摘要： A semiconductor device includes a silicon substrate having an active region, a memory transistor having a pair of source/drain regions and a gate electrode layer, a hard mask layer on the gate electrode layer having a plane pattern shape identical with that of the gate electrode layer, and plug conductive layers each electrically connected to each of the pair of source/drain regions. An extending direction of the active region is not perpendicular to that of the gate electrode layer, but is oblique. Upper surfaces of the hard mask layer and each of the plug conductive layers form substantially an identical plane. This can attain a semiconductor device allowing significant enlargement of a margin in a photolithographic process, suppression of an “aperture defect” as well as ensuring of a process tolerance of a “short” by decreasing a microloading effect, and decrease in a contact resistance, and a manufacturing method thereof.

摘要翻译： 半导体器件包括具有有源区的硅衬底，具有一对源极/漏极区和栅极电极层的存储晶体管，栅电极层上的硬掩模层具有与栅电极的平面图形相同的平面图形 层，并且插塞导电层，每个导电层电连接到该对源/漏区中的每一个。 有源区的延伸方向不与栅电极层的延伸方向垂直，而是倾斜。 硬掩模层和每个插塞导电层的上表面基本上形成相同的平面。 这可以获得允许在光刻工艺中显着增大余量的半导体器件，抑制“孔径缺陷”以及通过减小微负载效应来确保“短路”的工艺公差，以及降低接触电阻， 及其制造方法。

公开(公告)号：US07709324B2

公开(公告)日：2010-05-04

申请号：US11544616

申请日：2006-10-10

申请人： Shigeru Shiratake

发明人： Shigeru Shiratake

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/66621 ,  H01L21/823437 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10894

摘要： Gate trenches 108 are formed in a memory cell region M using a silicon nitride film 103 as a mask in a state in which the semiconductor substrate 100 in a P-type peripheral circuit region P and an N-type peripheral circuit region N is covered by a gate insulating film 101s, a protective film 102, and the silicon nitride film 103. A gate insulating film 109 is then formed on the inner walls of the gate trenches 108, and a silicon film 110 that includes an N-type impurity is embedded in the gate trenches 108. The silicon nitride film 103 is then removed, and a non-doped silicon film is formed on the entire surface, after which a P-type impurity is introduced into the non-doped silicon film on region P, and an N-type impurity is introduced into the non-doped silicon film on regions M and N.

摘要翻译： 在P型外围电路区域P中的半导体衬底100和N型外围电路区域N被覆盖的状态下，使用氮化硅膜103作为掩模，在存储单元区域M中形成栅极沟槽108 栅极绝缘膜101s，保护膜102和氮化硅膜103.然后在栅极沟槽108的内壁上形成栅极绝缘膜109，并且嵌入包括N型杂质的硅膜110 然后去除氮化硅膜103，并且在整个表面上形成非掺杂硅膜，之后将P型杂质引入到区域P上的非掺杂硅膜中，以及 在区域M和N上的非掺杂硅膜中引入N型杂质。

公开(公告)号：US20050077560A1

公开(公告)日：2005-04-14

申请号：US10961210

申请日：2004-10-12

申请人： Shigeru Shiratake

发明人： Shigeru Shiratake

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108 ,  H01L29/94

CPC分类号： H01L27/10855 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10888 ,  H01L27/10894

摘要： A semiconductor device includes a silicon substrate having an active region, a memory transistor having a pair of source/drain regions and a gate electrode layer, a hard mask layer on the gate electrode layer having a plane pattern shape identical with that of the gate electrode layer, and plug conductive layers each electrically connected to each of the pair of source/drain regions. An extending direction of the active region is not perpendicular to that of the gate electrode layer, but is oblique. Upper surfaces of the hard mask layer and each of the plug conductive layers form substantially an identical plane. This can attain a semiconductor device allowing significant enlargement of a margin in a photolithographic process, suppression of an “aperture defect” as well as ensuring of a process tolerance of a “short” by decreasing a microloading effect, and decrease in a contact resistance, and a manufacturing method thereof.

摘要翻译： 半导体器件包括具有有源区的硅衬底，具有一对源极/漏极区和栅极电极层的存储晶体管，栅电极层上的硬掩模层具有与栅电极的平面图形相同的平面图形 层，并且插塞导电层，每个导电层电连接到该对源/漏区中的每一个。 有源区的延伸方向不与栅电极层的延伸方向垂直，而是倾斜。 硬掩模层和每个插塞导电层的上表面基本上形成相同的平面。 这可以获得允许在光刻工艺中显着增大余量的半导体器件，抑制“孔径缺陷”以及通过减小微负载效应来确保“短路”的工艺公差，以及降低接触电阻， 及其制造方法。

公开(公告)号：US06667505B2

公开(公告)日：2003-12-23

申请号：US10123165

申请日：2002-04-17

申请人： Koichiro Narimatsu ,  Shigeru Shiratake

发明人： Koichiro Narimatsu ,  Shigeru Shiratake

IPC分类号： H01L27108

CPC分类号： H01L27/10855 ,  H01L27/0207 ,  H01L28/90

摘要： A semiconductor device includes a capacitor formed to have an approximately elliptical cross-sectional shape and extending upwards from upper surface of each said storage node contact. When an arrangement of capacitors is seen vertically from above, rows of capacitors are formed such that, along direction of a major axis of the approximate ellipse, a plurality of capacitors are aligned with regular intervals. When arbitrary one of said capacitor rows is taken as a first capacitor row, a second capacitor row is arranged in parallel therewith, and the capacitors in the first capacitor row and the second capacitor row are aligned out of phase with each other by length corresponding approximately to a sum of width of one transfer gate and width of one space between transfer gates.

摘要翻译： 半导体器件包括形成为具有大致椭圆形横截面形状并从每个所述存储节点接触件的上表面向上延伸的电容器。 当从上方观察电容器的布置时，形成电容器行，使得沿着近似椭圆的长轴的方向，多个电容器以规则的间隔对准。 当将所述电容器行中的任意一个作为第一电容器行时，与其并联布置第二电容器行，并且第一电容器行和第二电容器行中的电容器彼此相位相差大约对应的长度 到一个传输门的宽度和传输门之间的一个空间的宽度之和。

公开(公告)号：US6033971A

公开(公告)日：2000-03-07

申请号：US160379

申请日：1998-09-25

申请人： Kaoru Motonami ,  Shigeru Shiratake ,  Hiroshi Matsuo ,  Yuichi Yokoyama ,  Kenji Morisawa ,  Ritsuko Gotoda ,  Takaaki Murakami ,  Satoshi Hamamoto ,  Kenji Yasumura ,  Yasuyoshi Itoh

发明人： Kaoru Motonami ,  Shigeru Shiratake ,  Hiroshi Matsuo ,  Yuichi Yokoyama ,  Kenji Morisawa ,  Ritsuko Gotoda ,  Takaaki Murakami ,  Satoshi Hamamoto ,  Kenji Yasumura ,  Yasuyoshi Itoh

IPC分类号： H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234

CPC分类号： H01L21/823475 ,  H01L21/76205 ,  H01L21/7621 ,  H01L21/76216

摘要： There are provided a semiconductor device, which includes an element isolating oxide film having a good upper flatness, and a method of manufacturing the same. Assuming that t.sub.G represents a thickness of a gate electrode layer 6, a height t.sub.U to an upper surface of a thickest portion of element isolating oxide film 4 from an upper surface of a gate insulating film 5 and an acute angle .theta.i defined between the upper surfaces of element isolating oxide film 4 and gate insulating film are set within ranges expressed by the formula of {.theta.i, t.sub.U .linevert split.0.ltoreq..theta.i.ltoreq.56.6.degree., 0.ltoreq.t.sub.U .ltoreq.0.82t.sub.G }. Thereby, an unetched portion does not remain at an etching step for patterning the gate electrode layer to be formed later. This prevents short-circuit of the gate electrode. Since the element isolating oxide film has the improved flatness, a quantity of overetching in an active region can be reduced at a step of patterning the gate electrode. This prevents shaving of the gate insulating film and the underlying substrate surface.

摘要翻译： 提供了一种半导体器件，其包括具有良好的上部平坦度的元件隔离氧化物膜及其制造方法。 假设tG表示栅电极层6的厚度，从栅极绝缘膜5的上表面到元件隔离氧化膜4的最厚部分的上表面的高度tU和在上表面之间限定的锐角θi 元件隔离氧化膜4和栅极绝缘膜的表面被设置在由公式{θi，tU + 5443 0 = 0.82tG}表示的范围内 。 因此，未蚀刻部分不保留在用于图形化稍后形成的栅极电极层的蚀刻步骤。 这防止了栅电极的短路。 由于元件隔离氧化物膜具有改善的平坦度，所以在图案化栅极电极的步骤中可以减少活性区域中的过蚀刻量。 这防止了栅极绝缘膜和下面的衬底表面的剃刮。

公开(公告)号：US5831323A

公开(公告)日：1998-11-03

申请号：US601662

申请日：1996-02-14

申请人： Kaoru Motonami ,  Shigeru Shiratake ,  Hiroshi Matsuo ,  Yuichi Yokoyama ,  Kenji Morisawa ,  Ritsuko Gotoda ,  Takaaki Murakami ,  Satoshi Hamamoto ,  Kenji Yasumura ,  Yasuyoshi Itoh

发明人： Kaoru Motonami ,  Shigeru Shiratake ,  Hiroshi Matsuo ,  Yuichi Yokoyama ,  Kenji Morisawa ,  Ritsuko Gotoda ,  Takaaki Murakami ,  Satoshi Hamamoto ,  Kenji Yasumura ,  Yasuyoshi Itoh

IPC分类号： H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/00

CPC分类号： H01L21/823475 ,  H01L21/76205 ,  H01L21/7621 ,  H01L21/76216

摘要： There are provided a semiconductor device, which includes an element isolating oxide film having a good upper flatness, and a method of manufacturing the same. Assuming that t.sub.G represents a thickness of a gate electrode layer 6, a height t.sub.U to an upper surface of a thickest portion of element isolating oxide film 4 from an upper surface of a gate insulating film 5 and an acute angle .theta.i defined between the upper surfaces of element isolating oxide film 4 and gate insulating film are set within ranges expressed by the formula of {.theta.i, t.sub.U .linevert split.0.ltoreq..theta.i.ltoreq.56.6.degree., 0.ltoreq.t.sub.U .ltoreq.0.82t.sub.G }. Thereby, an unetched portion does not remain at an etching step for patterning the gate electrode layer to be formed later. This prevents short-circuit of the gate electrode. Since the element isolating oxide film has the improved flatness, a quantity of overetching in an active region can be reduced at a step of patterning the gate electrode. This prevents shaving of the gate insulating film and the underlying substrate surface.