公开(公告)号：US20190280198A1

公开(公告)日：2019-09-12

申请号：US16419165

申请日：2019-05-22

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Renu WHIG ,  Jijun SUN ,  Nicholas RIZZO ,  Jon SLAUGHTER ,  Dimitri HOUSSAMEDDINE ,  Frederick MANCOFF

IPC: H01L43/12 ,  G11C11/16 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A magnetoresistive element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer, having a high-iron alloy interface region located along a surface of the free magnetic layer, wherein the high-iron alloy interface region has at least 50% iron by atomic composition, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. The magnetoresistive element further includes a second dielectric, having a first surface that is in contact with the surface of the free magnetic layer, and an electrode, disposed between the second dielectric and a conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion having at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.

公开(公告)号：US20190214070A1

公开(公告)日：2019-07-11

申请号：US16358414

申请日：2019-03-19

Applicant: Everspin Technologies, Inc.

Inventor： Jason JANESKY ,  Syed M. ALAM ,  Dimitri HOUSSAMEDDINE ,  Mark DEHERREA

IPC: G11C11/16 ,  G11C17/16 ,  G11C29/50 ,  G11C29/02 ,  G11C29/12

CPC classification number: G11C11/1673 ,  G11C11/16 ,  G11C11/1675 ,  G11C17/16 ,  G11C29/021 ,  G11C29/023 ,  G11C29/026 ,  G11C29/028 ,  G11C29/12 ,  G11C29/50

Abstract: Techniques and circuits for testing and configuring bias voltage or bias current for write operations in memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation.

公开(公告)号：US20190156878A1

公开(公告)日：2019-05-23

申请号：US16217185

申请日：2018-12-12

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Thomas ANDRE ,  Dimitri HOUSSAMEDDINE ,  Syed M. ALAM ,  Jon SLAUGHTER ,  Chitra SUBRAMANIAN

IPC: G11C11/16

Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.