公开(公告)号：US20200235289A1

公开(公告)日：2020-07-23

申请号：US16251230

申请日：2019-01-18

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Thomas ANDRE ,  Frederick MANCOFF ,  Sumio IKEGAWA

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16

Abstract: The present disclosure is drawn to, among other things, a magnetoresistive memory. The magnetoresistive memory comprises a plurality of magnetoresistive memory devices, wherein each magnetoresistive memory device includes a fixed magnetic region, a free magnetic region, and an intermediate region disposed in between the fixed and free magnetic regions. The magnetoresistive memory further comprises a first conductor extending adjacent each magnetoresistive memory device of the plurality of magnetoresistive devices, wherein the first conductor is in electrical contact with the free magnetic region of each magnetoresistive memory device.

公开(公告)号：US20180122495A1

公开(公告)日：2018-05-03

申请号：US15852678

申请日：2017-12-22

Applicant: Everspin Technologies Inc.

Inventor： Thomas ANDRE ,  Jon SLAUGHTER ,  Dimitri HOUSSAMEDDINE ,  Syed M. ALAM

IPC: G11C29/50 ,  G11C11/16 ,  G06F11/08 ,  G06F11/10 ,  G11C29/04

CPC classification number: G11C29/50 ,  G06F11/08 ,  G06F11/1048 ,  G11C11/1673 ,  G11C2029/0411

Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.

公开(公告)号：US20170263300A1

公开(公告)日：2017-09-14

申请号：US15605508

申请日：2017-05-25

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Thomas ANDRE ,  Dimitri HOUSSAMEDDINE ,  Syed M. ALAM ,  Jon SLAUGHTER ,  Chitra SUBRAMANIAN

IPC: G11C11/16 ,  G06F12/0804

CPC classification number: G11C11/1675 ,  G06F12/0804 ,  G11C11/1677 ,  Y02D10/13

Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.

公开(公告)号：US20200286950A1

公开(公告)日：2020-09-10

申请号：US16881958

申请日：2020-05-22

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph NAGEL ,  Sanjeev AGGARWAL ,  Thomas ANDRE ,  Sarin A. DESHPANDE

IPC: H01L27/22 ,  H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  H01L43/02

Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.

公开(公告)号：US20200235288A1

公开(公告)日：2020-07-23

申请号：US16744963

申请日：2020-01-16

Applicant: Everspin Technologies, Inc.

Inventor： Sumio IKEGAWA ,  Han Kyu LEE ,  Sanjeev AGGARWAL ,  Jijun SUN ,  Syed M. ALAM ,  Thomas ANDRE

IPC: H01L43/04 ,  H01L27/22 ,  H01L43/06 ,  H01L43/10 ,  H01L43/14

Abstract: The present disclosure is drawn to, among other things, a magnetoresistive device and a magnetoresistive memory comprising a plurality of such magnetoresistive devices. In some aspects, a magnetoresistive device may include a magnetically fixed region, a magnetically free region above or below the magnetically fixed region, and an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material. The magnetoresistive device may also include encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material.

公开(公告)号：US20190087250A1

公开(公告)日：2019-03-21

申请号：US16174557

申请日：2018-10-30

Applicant: Everspin Technologies, Inc.

Inventor： Jon SLAUGHTER ,  Dimitri HOUSSAMEDDINE ,  Thomas ANDRE ,  Syed M. ALAM

IPC: G06F11/07 ,  G11C11/16

Abstract: A method is provided for healing reset errors for a magnetic memory using destructive read with selective write-back, including for example, a self-referenced read of spin-torque bits in an MRAM. Memory cells are prepared for write back by one of identifying memory cells determined in error using an error correcting code and inverting the inversion bit for those memory cells determined in error identifying memory cells determined in error using an error correcting code and resetting a portion of the memory cells to the first state; and resetting one or more memory cells to the first state.

公开(公告)号：US20170301384A1

公开(公告)日：2017-10-19

申请号：US15636970

申请日：2017-06-29

Applicant: Everspin Technologies, Inc.

Inventor： Thomas ANDRE ,  Syed M. ALAM ,  Chitra SUBRAMANIAN

IPC: G11C11/16 ,  G11C7/06 ,  G11C7/02 ,  G11C13/00

CPC classification number: G11C11/1675 ,  G11C7/02 ,  G11C7/065 ,  G11C11/16 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0057 ,  G11C2207/002

Abstract: An apparatus used in a self-referenced read of a memory bit cell includes circuitry including a plurality of transistors that includes an NMOS-follower transistor for applying a read voltage to a first end of the bit cell. An offset current is applied by an offset current transistor. A transmission gate allows for isolation of a capacitor used to store a sample voltage corresponding to the read voltage applied across the memory bit cell.

公开(公告)号：US20230100514A1

公开(公告)日：2023-03-30

申请号：US18045539

申请日：2022-10-11

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph NAGEL ,  Sanjeev AGGARWAL ,  Thomas ANDRE ,  Sarin A. DESHPANDE

IPC: H01L27/22 ,  H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  H01L43/02

Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.

公开(公告)号：US20190199375A1

公开(公告)日：2019-06-27

申请号：US16288664

申请日：2019-02-28

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Thomas ANDRE

IPC: H03M13/29 ,  G06F11/10

CPC classification number: H03M13/2906 ,  G06F11/1012 ,  G06F11/1076

Abstract: In some examples, a memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page, such that a first level of error correction may be performed by the memory device on each of the ECC words associated with a page and a second level of error correction may be performed on the data output by each of the input/output pads during a particular period of time. Each of the one or more input/output pads of the memory device may be configured to provide only one bit of data per ECC word to an external source during an access from an external source.

公开(公告)号：US20190043921A1

公开(公告)日：2019-02-07

申请号：US16143088

申请日：2018-09-26

Applicant: Everspin Technologies, Inc.

Inventor： Thomas ANDRE ,  Sanjeev AGGARWAL ,  Kerry Joseph NAGEL ,  Sarin A. DESHPANDE

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02 ,  G11C11/16 ,  H01L43/08

CPC classification number: H01L27/222 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.