公开(公告)号：US20210118948A1

公开(公告)日：2021-04-22

申请号：US17134865

申请日：2020-12-28

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph NAGEL ,  Sanjeev AGGARWAL ,  Thomas ANDRE ,  Sarin A. DESHPANDE

IPC: H01L27/22 ,  H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  H01L43/02

Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.

公开(公告)号：US20190221247A1

公开(公告)日：2019-07-18

申请号：US16251882

申请日：2019-01-18

Applicant: Everspin Technologies, Inc.

Inventor： Thomas ANDRE ,  Syed M. ALAM

IPC: G11C11/16 ,  G11C11/4094 ,  G11C7/12 ,  G06F11/10

Abstract: In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to reduce power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving a global word line to a first voltage. Driving the global word line to a first voltage results in a second voltage passed to the word lines. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell.

公开(公告)号：US20190221242A1

公开(公告)日：2019-07-18

申请号：US16252067

申请日：2019-01-18

Applicant: Everspin Technologies, Inc.

Inventor： Thomas ANDRE ,  Syed M. ALAM ,  Frederick NEUMEYER

IPC: G11C5/14 ,  G11C11/16 ,  H01L27/22 ,  H01L43/08

CPC classification number: G11C5/147 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/224 ,  H01L27/228 ,  H01L43/08

Abstract: The present disclosure is drawn to, among other things, a magnetic memory. The magnetic memory comprises a first common line, a second common line, and a memory cell. The magnetic memory further includes a bias voltage generation circuit and a voltage driver. The bias voltage generation circuit and the voltage driver are configured to provide driving voltages to the memory cell during access operations.

公开(公告)号：US20190156878A1

公开(公告)日：2019-05-23

申请号：US16217185

申请日：2018-12-12

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Thomas ANDRE ,  Dimitri HOUSSAMEDDINE ,  Syed M. ALAM ,  Jon SLAUGHTER ,  Chitra SUBRAMANIAN

IPC: G11C11/16

Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.

公开(公告)号：US20190088306A1

公开(公告)日：2019-03-21

申请号：US16192344

申请日：2018-11-15

Applicant: Everspin Technologies, Inc.

Inventor： Thomas ANDRE ,  Syed M. ALAM

IPC: G11C11/16 ,  G06F12/0806 ,  G11C7/22 ,  G11C7/10 ,  G06F12/0879 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/419 ,  G11C11/4094 ,  G11C11/56

Abstract: In some examples, a memory device is configured with a reduced command set and a variable burst length. In some instances, the variable burst length defines a page size associated with data to be loaded into a cache. In other instances, the variable burst length may be set on the fly per read/write command and, in some cases, the burst length may be utilized to define the page size associated with the read/write command.

公开(公告)号：US20170337959A1

公开(公告)日：2017-11-23

申请号：US15672469

申请日：2017-08-09

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Thomas ANDRE

IPC: G11C11/16 ,  H01L43/02 ,  G11C13/00 ,  G06F11/10 ,  G11C29/52 ,  H01L43/08 ,  H01L27/22 ,  G11C5/06

CPC classification number: G11C11/1673 ,  G06F11/1068 ,  G09C1/00 ,  G11C5/06 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0026 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C14/0081 ,  G11C14/009 ,  G11C29/52 ,  G11C2213/75 ,  G11C2213/77 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H04L9/0866

Abstract: In some examples, a nonvolatile storage element may be configured to store a state or value during a low power or powered down period of a circuit. For example, the nonvolatile storage element may include a bridge of resistive elements that have a resistive state that may be configured by applying voltages to multiple drive paths. A sense amplifier may be connected to the bridge in order to resolve a voltage differential associated with the bridge to ether power or ground and, thereby determine the state associated with on the nonvolatile storage element.