公开(公告)号：US5553017A

公开(公告)日：1996-09-03

申请号：US310836

申请日：1994-09-22

Applicant: Paolo Ghezzi ,  Federico Pio ,  Carlo Riva

Inventor： Paolo Ghezzi ,  Federico Pio ,  Carlo Riva

IPC: G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC classification number: H01L27/11521 ,  H01L27/11558

Abstract: A method for producing electrically erasable and programmable read-only memory cells with a single polysilicon level, including the use of a sacrificial layer of silicon oxide to produce a high-thickness silicon oxide layer on the active area. The active area of the cell is protected from heavy source and drain implantation in order to improve reliability.

Abstract translation: 一种用于制造具有单个多晶硅级别的电可擦除和可编程只读存储器单元的方法，包括使用氧化硅牺牲层在有源区上产生高厚度氧化硅层。 为了提高可靠性，保护电池的有源区域免受重的源极和漏极注入。

公开(公告)号：US08248851B1

公开(公告)日：2012-08-21

申请号：US12628073

申请日：2009-11-30

Applicant: Federico Pio

Inventor： Federico Pio

IPC: G11C16/04

CPC classification number: G11C11/5642 ,  G11C16/26 ,  G11C16/3404

Abstract: A system, apparatus, and method to read a memory cell of a memory device is described. The method includes biasing a drain select line (DSL), a source select line (SSL), and unaddressed wordlines of a memory block to a pass voltage to set the DSL, SSL, and unselected word lines into a conducting status; applying a source reading voltage to a source node of the source line; biasing a wordline coupled to the memory cell to a reading voltage; and evaluating the voltage of the bit line.The logical status of the addressed memory cell is based on sensing the bit line voltage during a charging phase of the bit line.

Abstract translation: 描述了读取存储器件的存储器单元的系统，装置和方法。 该方法包括将漏极选择线（DSL），源选择线（SSL）和存储器块的未寻址字线偏置到通过电压以将DSL，SSL和未选择的字线设置为导通状态; 将源读取电压施加到源极线的源节点; 将耦合到所述存储器单元的字线偏压到读取电压; 并评估位线的电压。 寻址的存储单元的逻辑状态基于在位线的充电阶段期间感测位线电压。

公开(公告)号：US20120127807A1

公开(公告)日：2012-05-24

申请号：US12949728

申请日：2010-11-18

Applicant: Federico Pio

Inventor： Federico Pio

IPC: G11C5/14 ,  G06F12/00

CPC classification number: G11C5/147 ,  G06F12/0246 ,  G06F21/60 ,  G06F2212/7204 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C11/5621 ,  G11C11/5671 ,  G11C14/0063 ,  G11C14/009 ,  G11C16/0408 ,  G11C16/06 ,  G11C16/107 ,  G11C16/12 ,  G11C16/26 ,  G11C16/30

Abstract: Subject matter disclosed herein relates to techniques to operate memory.

Abstract translation: 本文公开的主题涉及操作存储器的技术。

公开(公告)号：US20120126196A1

公开(公告)日：2012-05-24

申请号：US12951304

申请日：2010-11-22

Applicant: Federico Pio

Inventor： Federico Pio

IPC: H01L45/00 ,  H01L21/02

CPC classification number: H01L45/1286 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/16 ,  H01L45/1675

Abstract: A substantially planar heater for a phase change memory may taper as it extends upwardly to contact a chalcogenide layer. As a result, the contact area between heater and chalcogenide is reduced. This reduced contact area can reduce power consumption in some embodiments.

Abstract translation: 用于相变存储器的基本上平面的加热器可以向上延伸以逐渐接触硫族化物层。 结果，加热器和硫族化物之间的接触面积减小了。 在一些实施例中，这种减小的接触面积可以降低功耗。

公开(公告)号：US07345905B2

公开(公告)日：2008-03-18

申请号：US11367707

申请日：2006-03-02

Applicant: Federico Pio ,  Efrem Bolandrina ,  Daniele Vimercati

Inventor： Federico Pio ,  Efrem Bolandrina ,  Daniele Vimercati

IPC: G11C17/00

CPC classification number: G11C11/5642 ,  G11C16/32 ,  G11C2211/5634

Abstract: A memory device includes a plurality of memory cells and a comparison circuit that compares a set of selected memory cells with at least one reference cell having a threshold voltage. The comparison circuit includes a bias circuit that applies a biasing voltage having a substantially monotone time pattern to the selected memory cells and to the at least one reference cell, sense amplifiers that detect the reaching of a comparison current by a cell current of each selected memory cell and by a reference current of each reference cell, a logic unit that determines a condition of each selected memory cell according to a temporal relation of the reaching of the comparison current by the corresponding cell current and by the at least one reference current, and a time shift structure that time shifts at least one of said detections according to at least one predefined interval to emulate the comparison with at least one further reference cell having a further threshold voltage.

Abstract translation: 存储器件包括多个存储器单元和比较电路，其将所选择的存储器单元组与至少一个具有阈值电压的参考单元进行比较。 比较电路包括偏置电路，该偏置电路将具有基本上单调的时间图案的偏置电压施加到所选择的存储器单元和至少一个参考单元，检测放大器，其通过每个选择的存储器的单元电流检测比较电流的到达 单元和每个参考单元的参考电流;逻辑单元，其根据比较电流到达相应的单元电流和至少一个参考电流的时间关系来确定每个选择的存储单元的状态;以及 时移结构，其根据至少一个预定间隔时间移动至少一个所述检测，以模拟与具有另一阈值电压的至少一个另外的参考小区的比较。

公开(公告)号：US06852596B2

公开(公告)日：2005-02-08

申请号：US09779956

申请日：2001-02-09

Applicant: Federico Pio

Inventor： Federico Pio

IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L21/336

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11524

Abstract: An electronic memory circuit comprises a matrix of EEPROM memory cells. Each memory cell includes a MOS floating gate transistor and a selection transistor. The matrix includes a plurality of rows and columns, with each row being provided with a word line and each column comprising a bit line organized in line groups so as to group the matrix cells in bytes, each of which has an associated control gate line. A pair of cells have a common source region, and each cell symmetrically provided with respect to this common source region has a common control gate region.

Abstract translation: 电子存储器电路包括EEPROM存储器单元的矩阵。 每个存储单元包括MOS浮栅晶体管和选择晶体管。 矩阵包括多个行和列，每行具有字线，并且每列包括以线组组织的位线，以便以字节为单位对矩阵单元进行分组，每个矩阵单元具有关联的控制栅极线。 一对单元具有公共源极区域，并且相对于该公共源极区域对称地设置的每个单元具有公共控制栅极区域。

公开(公告)号：US06548354B2

公开(公告)日：2003-04-15

申请号：US09796757

申请日：2001-02-28

Applicant: Roberta Bottini ,  Giovanna Dalla Libera ,  Bruno Vajana ,  Federico Pio

Inventor： Roberta Bottini ,  Giovanna Dalla Libera ,  Bruno Vajana ,  Federico Pio

IPC: H01L21336

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11558

Abstract: A process for manufacturing a semiconductor memory device includes double polysilicon level non-volatile memory cells and shielded single polysilicon level non-volatile memory cells in the same semiconductor material chip. A first memory cell includes a MOS transistor having a first gate electrode and a second gate electrode superimposed and respectively formed by definition in a first and a second layer of conductive material. A second memory cell is shielded by a layer of shielding material for preventing the information stored in the second memory cell from being accessible from the outside. The second memory cell includes a MOS transistor with a floating gate electrode formed simultaneously with the first gate electrode of the first cell by definition of the first layer of conductive material. The layer of shielding material is formed by definition of the second layer of conductive material.

Abstract translation: 半导体存储器件的制造方法包括双重多晶硅级非易失性存储单元和同一半导体材料芯片中的屏蔽单个多晶硅级非易失性存储单元。 第一存储单元包括MOS晶体管，其具有叠加并分别形成在第一和第二导电材料层中的第一栅电极和第二栅电极。 第二存储单元被屏蔽材料层屏蔽，以防止存储在第二存储单元中的信息可从外部访问。 第二存储单元包括具有通过第一导电材料层与第一单元的第一栅电极同时形成的浮栅的MOS晶体管。 屏蔽材料层通过第二层导电材料的定义形成。

公开(公告)号：US06535431B1

公开(公告)日：2003-03-18

申请号：US09552933

申请日：2000-04-20

Applicant: Federico Pio ,  Enrico Gomiero ,  Paola Zuliani

Inventor： Federico Pio ,  Enrico Gomiero ,  Paola Zuliani

IPC: G11C1604

CPC classification number: G11C16/12 ,  G11C16/0433 ,  G11C16/30

Abstract: The invention relates to a method of adjusting the erase/program voltage in semiconductor non-volatile memories. The memories are formed of at least one matrix of memory cells having a floating gate, a control gate, and drain and source terminals, and are organized by the byte in rows and columns, each byte comprising a group of cells having respective control gates connected in parallel with one another to a common control line through a selection element of the byte switch type, and each cell being connected to a respective control column through a selection element of the bit switch type. Advantageously, a double adjustment is provided for the program voltage of the memory cells, whereby the program voltage during the erasing phase can be higher in modulo than the program voltage during the writing phase. This is achieved by providing respective adjusters connected between a program voltage generator and the cell matrix, or alternatively forming the bit switch element inside a well and the byte switch element directly in the substrate.

Abstract translation: 本发明涉及一种调整半导体非易失性存储器中擦除/编程电压的方法。 存储器由具有浮置栅极，控制栅极和漏极和源极端子的至少一个存储单元矩阵形成，并且由行和列中的字节组织，每个字节包括连接有相应控制栅极的一组单元 通过字节开关类型的选择元件彼此并行地连接到公共控制线，并且每个单元通过位开关类型的选择元件连接到相应的控制列。 有利地，为存储器单元的编程电压提供双重调整，由此在擦除阶段期间的编程电压可以比写入阶段期间的编程电压模数更高。 这通过提供连接在编程电压发生器和单元矩阵之间的相应调节器，或者可选地将阱内的位开关元件和字节开关元件直接放置在衬底中来实现。

公开(公告)号：US06387763B1

公开(公告)日：2002-05-14

申请号：US09442834

申请日：1999-11-18

Applicant: Federico Pio ,  Paola Zuliani

Inventor： Federico Pio ,  Paola Zuliani

IPC: H01L21336

CPC classification number: H01L29/1041 ,  H01L21/76202

Abstract: A field effect transistor having a variable doping profile is presented. The field effect transistor is integrated on a semiconductor substrate with a respective active area of the substrate including a source and drain region. A channel region is interposed between the source and drain regions and has a predefined nominal width. The effective width of the channel region is defined by a variable doping profile.

Abstract translation: 提出了具有可变掺杂分布的场效应晶体管。 场效应晶体管集成在具有源极和漏极区域的衬底的相应有源区域的半导体衬底上。 沟道区域介于源区和漏区之间并且具有预定义的标称宽度。 沟道区域的有效宽度由可变掺杂分布限定。

公开(公告)号：US06204531B1

公开(公告)日：2001-03-20

申请号：US09363429

申请日：1999-07-29

Applicant: Giovanna Dalla Libera ,  Federico Pio

Inventor： Giovanna Dalla Libera ,  Federico Pio

IPC: H01L29792

CPC classification number: H01L29/42324 ,  H01L27/115

Abstract: A semiconductor non-volatile memory device that includes memory cells and selection transistors. The memory cells each include a floating gate transistor having an active area, source and drain regions, a floating gate, and a control gate, and each of the floating gate transistors is serially coupled to one of the selection transistors. A contact to the control gate is located above the active area. In a preferred embodiment, the contact is substantially aligned with a central portion of the active area. A method for manufacturing a non-volatile memory device on a semiconductor substrate is also provided. According to the method, a poly1 layer is deposited, an interpoly dielectric layer is deposited above the poly1 layer, and a poly2 layer is deposited above the interpoly dielectric layer. A mask is provided to define the control gate, and a Self-Aligned poly2/interpoly/poly1 stack etching is used to define a gate stack structure that includes the control gate and the floating gate. The floating gate is defined using only the mask and the Self-Aligned poly2/interpoly/poly1 stack etching. In one preferred method, a contact to the control gate is formed above the active area.