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公开(公告)号：US06518628B1
公开(公告)日：2003-02-11
申请号：US09423864
申请日：1999-11-15
IPC分类号： H01L2976
CPC分类号： H01L27/0922
摘要： An integrated CMOS circuit arrangement and a method of manufacturing same, which includes both a first MOS transistor and a second MOS transistor complementary thereto, wherein one of the MOS transistors is arranged at the floor of a trench and the other is arranged at the principal surface of a semiconductor substrate. The MOS transistors are arranged relative to one another such that a current flow through the MOS transistors respectively occurs substantially parallel to a sidewall of the trench that is arranged between the MOS transistors.
摘要翻译： 一种集成CMOS电路装置及其制造方法，其包括第一MOS晶体管和与其互补的第二MOS晶体管，其中MOS晶体管中的一个布置在沟槽的底部，而另一个布置在主表面 的半导体衬底。 MOS晶体管相对于彼此布置，使得流过MOS晶体管的电流分别基本上平行于布置在MOS晶体管之间的沟槽的侧壁。
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公开(公告)号：US5998261A
公开(公告)日：1999-12-07
申请号：US973701
申请日：1997-12-08
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L27/11517 , H01L27/115
摘要： An electrically writable and erasable read-only memory cell arrangement fabricated in a semiconductor substrate, preferably of monocrystalline silicon, or in a silicon layer of an SOI substrate. A cell array with memory cells is provided on a main surface of the semiconductor substrate. Each memory cell comprises an MOS transistor, vertical to the main surface and comprising, in addition to the source/drain region and a channel region arranged in-between, a first dielectric, a floating gate, a second dielectric and a control gate. A plurality of essentially parallel strip-shaped trenches are provided in the cell array. The vertical MOS transistors are arranged on the flanks of the trenches. The memory cells are in each case arranged on opposite flanks of the trenches.
摘要翻译： PCT No.PCT / DE96 / 01117 Sec。 371 1997年12月8日第 102（e）日期1997年12月8日PCT提交1996年6月25日PCT公布。 第WO97 / 02599号公报 日期1997年1月23日在半导体衬底（优选单晶硅）或SOI衬底的硅层中制造的电可写和可擦除的只读存储单元布置。 具有存储单元的单元阵列设置在半导体基板的主表面上。 每个存储单元包括垂直于主表面的MOS晶体管，并且除了源极/漏极区域和布置在其之间的沟道区域之外还包括第一电介质，浮动栅极，第二电介质和控制栅极。 多个基本上平行的带状沟槽设置在单元阵列中。 垂直MOS晶体管布置在沟槽的侧面。 存储单元在每种情况下都布置在沟槽的相对侧面上。
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公开(公告)号：US5920099A
公开(公告)日：1999-07-06
申请号：US913332
申请日：1997-09-11
IPC分类号： H01L21/8246 , H01L27/112
CPC分类号： H01L27/1126 , H01L27/112
摘要： A read-only memory cell array has a plurality of individual memory cells which each have a MOS transistor and which are arranged in rows running in parallel. In this context, adjacent rows run alternately at the bottom of the longitudinal trenches (6) and between adjacent longitudinal trenches (6) respectively and are insulated with respect to one another. The read-only memory cell array can be manufactured by self-aligning process steps with an area of 2 F.sup.2 (F: minimum structure size) being required per memory cell.
摘要翻译： PCT No.PCT / DE96 / 00380 Sec。 371日期：1997年9月11日 102（e）1997年9月11日PCT PCT 1996年3月4日PCT公布。 公开号WO96 / 29739 日期1996年9月26日只读存储单元阵列具有多个单独的存储单元，每个单独存储单元具有MOS晶体管并且并行排列。 在这种情况下，相邻的行分别在纵向沟槽（6）的底部和相邻的纵向沟槽（6）之间交替地延伸并相对于彼此绝缘。 只读存储单元阵列可以通过每个存储单元需要2 F2（F：最小结构尺寸）面积的自对准工艺步骤来制造。
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14.发明授权Method of producing and arrangement containing self-amplifying dynamic MOS transistor memory cells 失效包含自放大动态MOS晶体管存储单元的制造和布置方法
公开(公告)号：US5710072A
公开(公告)日：1998-01-20
申请号：US737236
申请日：1996-11-18
IPC分类号： H01L27/08 , H01L21/8242 , H01L27/06 , H01L27/108 , H01L21/336
CPC分类号： H01L27/10844 , H01L27/0629 , H01L27/108
摘要： To produce an arrangement containing self-amplifying dynamic MOS transistor memory cells which each comprise a selection transistor, a memory transistor and a diode structure, the selection transistor and the memory transistor being connected in series via a common nodal point and the diode structure being connected between the common nodal point and the gate electrode (10) of the memory transistor, the selection transistor and the memory transistor are formed as vertical MOS transistors. For this purpose a vertical sequence of suitably doped zones (2, 3, 4) in which trenches (5, 6) are produced and which are provided with gate dielectric (7, 8) and gate electrode (9, 10) is produced, in particular, by LPCVD epitaxy or by molecular-beam epitaxy.
摘要翻译： PCT No.PCT / EP95 / 01656 Sec。 371日期：1996年11月18日 102（e）1996年11月18日PCT PCT 1995年5月2日PCT公布。 公开号WO95 / 31828 日期：1995年11月23日为了制造包含自放大动态MOS晶体管存储单元的布置，每个包括选择晶体管，存储晶体管和二极管结构，选择晶体管和存储晶体管通过公共节点串联连接， 二极管结构连接在存储晶体管的公共节点和栅电极（10）之间，选择晶体管和存储晶体管形成为垂直MOS晶体管。 为此，产生其中产生沟槽（5,6）并且设置有栅极电介质（7,8）和栅电极（9,10））的适当掺杂区（2,3,4）的垂直序列， 特别是通过LPCVD外延或通过分子束外延。
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公开(公告)号：US5920778A
公开(公告)日：1999-07-06
申请号：US913740
申请日：1997-09-23
IPC分类号： H01L21/8246 , H01L27/112
CPC分类号： H01L27/11273 , H01L27/112
摘要： In a read-only memory cell arrangement having first memory cells which contain a vertical MOS transistor, and having second memory cells which do not contain vertical MOS transistors, the memory cells are arranged along opposite flanks of strip-shaped parallel insulation trenches (16). The width of the insulation trenches (16) is preferably equal to their separation, so that the memory cell arrangement can be produced with a space requirement of 2F.sup.2 per memory cell, F being the minimum structure size in the respective technology.
摘要翻译： PCT No.PCT / DE96 / 00614 Sec。 371日期1997年9月23日 102（e）1997年9月23日PCT PCT 1996年4月9日PCT公布。 公开号WO96 / 3351300 日期1996年10月24日在具有包含垂直MOS晶体管的第一存储单元且具有不包含垂直MOS晶体管的第二存储单元的只读存储单元布置中，存储单元沿着带状平行的相对侧布置 绝缘沟槽（16）。 绝缘沟槽（16）的宽度优选等于它们的间隔，使得可以以每个存储单元的空间要求为2F2来生产存储单元布置，F是相应技术中的最小结构尺寸。
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16.发明授权Read-only-memory cell arrangement using vertical MOS transistors and gate dielectrics of different thicknesses and method for its production 失效使用垂直MOS晶体管和不同厚度的栅极电介质的只读存储单元布置及其制造方法
公开(公告)号：US5973373A
公开(公告)日：1999-10-26
申请号：US817630
申请日：1997-03-26
IPC分类号： H01L21/8247 , H01L21/8246 , H01L27/112 , H01L29/788 , H01L29/792 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L27/11273 , H01L27/112
摘要： A read-only-memory cell arrangement comprises memory cells, each having a vertical MOS transistor, in a substrate (21) made of semiconductor material, the various logic values (zero, one) being implemented by gate dielectrics (27, 28) of different thickness. The memory cell arrangement can preferably be produced in a silicon substrate, with a small number of process steps and a high packing density. The memory cell arrangement and a drive circuit for read-out can in this case be produced in an integrated manner.
摘要翻译： PCT No.PCT / DE95 / 01262 Sec。 371日期1997年3月26日 102（e）1997年3月26日PCT PCT 1995年9月14日PCT公布。 公开号WO96 / 10266 日期1996年4月4日只读存储单元布置包括在由半导体材料制成的衬底（21）中的每个具有垂直MOS晶体管的存储单元，各种逻辑值（零，1）由栅极电介质 27,28）。 存储单元布置可以优选地在硅衬底中制造，具有少量的工艺步骤和高的堆积密度。 在这种情况下，存储单元布置和用于读出的驱动电路可以以集成的方式产生。
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17.发明授权Electrically programmable memory cell arrangement and method for its manufacture 失效电可编程存储单元布置及其制造方法
公开(公告)号：US5959328A
公开(公告)日：1999-09-28
申请号：US779446
申请日：1997-01-07
IPC分类号： H01L21/8247 , H01L21/8246 , H01L29/788 , H01L29/792 , H01L29/76
CPC分类号： H01L27/11568 , H01L27/115
摘要： An electrically programmable memory cell arrangement has a plurality of individual memory cells that respectively has an MOS transistor with a gate dielectric with traps, and which are arranged in rows that run in parallel. Adjacent rows thereby respectively run in alternating fashion on the bottom of the longitudinal trenches (5) and between adjacent longitudinal trenches (5) and are insulated against one another. The memory cell arrangement can be manufactured by means of self-adjusting process steps with a surface requirement per memory cell of 2 F.sup.2 (F: minimum structural size).
摘要翻译： 电可编程存储单元布置具有多个单独的存储单元，它们分别具有带栅极电介质的MOS晶体管，并具有陷阱，并且它们排列成并行的行。 因此，相邻的行分别以纵向沟槽（5）的底部和相邻的纵向沟槽（5）之间交替地延伸并彼此绝缘。 可以通过自调整工艺步骤制造存储单元布置，每个存储单元的表面要求为2×2（F：最小结构尺寸）。
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公开(公告)号：US5736761A
公开(公告)日：1998-04-07
申请号：US645503
申请日：1996-05-14
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10876 , H01L27/10823
摘要： The DRAM cell arrangement has one vertical MOS transistor per memory cell, whose first source/drain region adjoins a trenched bitline (5), whose gate electrode (13) is connected with a trenched wordline and whose second source/drain region (3) adjoins a substrate main surface (1). A capacitor dielectric (16), which is in particular a ferroelectric or paraelectric layer, is arranged on at least the second source/drain region and a capacitor plate (17) is arranged on the dielectric, so that the second source/drain region (3) acts additionally as a memory node. The DRAM cell arrangement can be manufactured with a memory cell surface of 4 F.sup.2.
摘要翻译： DRAM单元布置对每个存储单元具有一个垂直MOS晶体管，其第一源极/漏极区域邻接沟槽位线（5），其栅极电极（13）与沟槽字线连接，并且其第二源极/漏极区域（3）邻接 基板主表面（1）。 至少在第二源极/漏极区域上布置有特别是铁电体或者顺电层的电容器电介质（16），并且电容器板（17）布置在电介质上，使得第二源极/漏极区域 3）另外作为存储器节点。 可以利用4F2的存储单元表面来制造DRAM单元布置。
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公开(公告)号：US06521935B2
公开(公告)日：2003-02-18
申请号：US10027524
申请日：2001-12-26
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10876 , H01L29/66666 , H01L29/7841 , H01L29/78642
摘要： A MOS transistor includes an upper source/drain region, a channel region, and a lower source/drain region that are stacked as layers one above the other and form a projection of a substrate. A gate dielectric adjoins a first lateral area of the projection. A gate electrode adjoins the gate dielectric. A conductive structure adjoins a second lateral area of the projection in the region of the channel region. The conductive structure adjoins the gate electrode.
摘要翻译： MOS晶体管包括上层堆叠的上源极/漏极区，沟道区和下源极/漏极区，并且形成衬底的突起。 栅极电介质邻接突起的第一横向区域。 栅电极邻接栅极电介质。 导电结构在通道区域的区域中毗邻突起的第二横向区域。 导电结构邻接栅电极。
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公开(公告)号：US6147376A
公开(公告)日：2000-11-14
申请号：US228611
申请日：1999-01-12
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10808
摘要： A memory cell contains at least one transistor and one capacitor connected to an upper bit line. The capacitor contains a first capacitor electrode arranged above the transistor, and is connected to the transistor. The upper bit line can be created in self-adjusted fashion on the basis of trenches which are of different widths, which extend transversely to one another, and which are arranged between the first capacitor electrodes. At least a part of each first capacitor electrode can be created from a layer which is structured by the trenches. Trenches can be narrowed by spacers.
摘要翻译： 存储单元包含至少一个晶体管和一个连接到高位线的电容器。 电容器包含布置在晶体管上方的第一电容器电极，并连接到晶体管。 基于具有不同宽度的沟槽彼此横向延伸并且布置在第一电容器电极之间的沟槽可以以自调节的方式创建高位线。 每个第一电容器电极的至少一部分可以由由沟槽构成的层产生。 沟槽可以通过间隔物变窄。
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