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公开(公告)号：US6147376A
公开(公告)日：2000-11-14
申请号：US228611
申请日：1999-01-12
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10808
摘要： A memory cell contains at least one transistor and one capacitor connected to an upper bit line. The capacitor contains a first capacitor electrode arranged above the transistor, and is connected to the transistor. The upper bit line can be created in self-adjusted fashion on the basis of trenches which are of different widths, which extend transversely to one another, and which are arranged between the first capacitor electrodes. At least a part of each first capacitor electrode can be created from a layer which is structured by the trenches. Trenches can be narrowed by spacers.
摘要翻译： 存储单元包含至少一个晶体管和一个连接到高位线的电容器。 电容器包含布置在晶体管上方的第一电容器电极，并连接到晶体管。 基于具有不同宽度的沟槽彼此横向延伸并且布置在第一电容器电极之间的沟槽可以以自调节的方式创建高位线。 每个第一电容器电极的至少一部分可以由由沟槽构成的层产生。 沟槽可以通过间隔物变窄。
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公开(公告)号：US06184045B2
公开(公告)日：2001-02-06
申请号：US09541952
申请日：2000-04-03
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L27/10808
摘要： A memory cell contains at least one transistor and one capacitor connected to an upper bit line. The capacitor contains a first capacitor electrode arranged above the transistor, and is connected to the transistor. The upper bit line can be created in self-adjusted fashion on the basis of trenches which are of different widths, which extend transversely to one another, and which are arranged between the first capacitor electrodes. At least a part of each first capacitor electrode can be created from a layer which is structured by the trenches. Trenches can be narrowed by spacers.
摘要翻译： 存储单元包含至少一个晶体管和一个连接到高位线的电容器。 电容器包含布置在晶体管上方的第一电容器电极，并连接到晶体管。 基于具有不同宽度的沟槽彼此横向延伸并且布置在第一电容器电极之间的沟槽可以以自调节的方式创建高位线。 每个第一电容器电极的至少一部分可以由由沟槽构成的层产生。 沟槽可以通过间隔物变窄。
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公开(公告)号：US5817552A
公开(公告)日：1998-10-06
申请号：US635526
申请日：1996-04-22
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10876 , H01L27/10823
摘要： For each storage cell, the DRAM cell arrangement has a vertical MOS transistor, the first source/drain region of which is connected to a memory node of a storage capacitor, the channel region of which is annularly enclosed by a gate electrode and the second source/drain region of which is connected to a buried bit line. The DRAM cell arrangement can be produced with a storage-cell area of 4F.sup.2 by using only two masks, F being the minimum producible structure size in the respective technology.
摘要翻译： 对于每个存储单元，DRAM单元布置具有垂直MOS晶体管，其第一源极/漏极区域连接到存储电容器的存储器节点，其存储电容器的沟道区域被栅电极环形地包围，并且第二源极 漏极区连接到埋地位线。 可以通过仅使用两个掩模来制造具有4F2的存储单元面积的DRAM单元布置，F是相应技术中的最小可生产结构尺寸。
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4.发明授权Method for manufacturing an integrated circuit arrangement having at least one MOS transistor 有权一种用于制造具有至少一个MOS晶体管的集成电路装置的方法公开(公告)号：US06274431B1
公开(公告)日：2001-08-14
申请号：US09301108
申请日：1999-04-28
IPC分类号： H01L2976
CPC分类号： H01L29/7827 , H01L21/823487 , H01L27/088 , H01L29/1037 , H01L29/4236 , H01L29/66666
摘要： An integrated circuit arrangement contains an MOS transistor surrounded by an insulation structure, the source and drain thereof being arranged laterally and in different depths. A channel thereof proceeds essentially perpendicular to the surface of the circuit arrangement. Since the channel length is determined by etching or by growing a layer, channel lengths as short as less than 50 nm can be realized. For the manufacture, most of the masks of the traditional circuit arrangements in which planar transistors are integrated are employed, this significantly facilitating incorporation into the semiconductor manufacture.
摘要翻译： 集成电路装置包含由绝缘结构围绕的MOS晶体管，其源极和漏极横向排列并且在不同的深度。 其通道基本上垂直于电路装置的表面。 由于通过蚀刻或通过生长层来确定沟道长度，所以可以实现短于小于50nm的沟道长度。 为了制造，采用其中集成平面晶体管的传统电路布置的大多数掩模，这显着地有助于结合到半导体制造中。
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5.发明授权Integrated circuit arrangement having at least one MOS transistor manufactured by use of a planar transistor layout 失效具有通过使用平面晶体管布局制造的至少一个MOS晶体管的集成电路装置
公开(公告)号：US6066876A
公开(公告)日：2000-05-23
申请号：US65173
申请日：1998-04-23
IPC分类号： H01L21/336 , H01L21/8234 , H01L27/088 , H01L29/10 , H01L29/423 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/7827 , H01L21/823487 , H01L27/088 , H01L29/1037 , H01L29/66666 , H01L29/4236
摘要： An integrated circuit arrangement contains an MOS transistor surrounded by an insulation structure, the source and drain thereof being arranged laterally and in different depths. A channel thereof proceeds essentially perpendicular to the surface of the circuit arrangement. Since the channel length is determined by etching or by growing a layer, channel lengths as short as less than 50 nm can be realized. For the manufacture, most of the masks of the traditional circuit arrangements in which planar transistors are integrated are employed, this significantly facilitating incorporation into the semiconductor manufacture.
摘要翻译： 集成电路装置包含由绝缘结构包围的MOS晶体管，其源极和漏极横向设置在不同的深度。 其通道基本上垂直于电路装置的表面。 由于通过蚀刻或通过生长层来确定沟道长度，所以可以实现短于小于50nm的沟道长度。 为了制造，采用其中集成平面晶体管的传统电路布置的大多数掩模，这显着地有助于结合到半导体制造中。
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公开(公告)号：US5736761A
公开(公告)日：1998-04-07
申请号：US645503
申请日：1996-05-14
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10876 , H01L27/10823
摘要： The DRAM cell arrangement has one vertical MOS transistor per memory cell, whose first source/drain region adjoins a trenched bitline (5), whose gate electrode (13) is connected with a trenched wordline and whose second source/drain region (3) adjoins a substrate main surface (1). A capacitor dielectric (16), which is in particular a ferroelectric or paraelectric layer, is arranged on at least the second source/drain region and a capacitor plate (17) is arranged on the dielectric, so that the second source/drain region (3) acts additionally as a memory node. The DRAM cell arrangement can be manufactured with a memory cell surface of 4 F.sup.2.
摘要翻译： DRAM单元布置对每个存储单元具有一个垂直MOS晶体管，其第一源极/漏极区域邻接沟槽位线（5），其栅极电极（13）与沟槽字线连接，并且其第二源极/漏极区域（3）邻接 基板主表面（1）。 至少在第二源极/漏极区域上布置有特别是铁电体或者顺电层的电容器电介质（16），并且电容器板（17）布置在电介质上，使得第二源极/漏极区域 3）另外作为存储器节点。 可以利用4F2的存储单元表面来制造DRAM单元布置。
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7.发明授权Method for production of a read-only-memory cell arrangement having vertical MOS transistors 失效用于制造具有垂直MOS晶体管的只读存储单元布置方法
公开(公告)号：US5744393A
公开(公告)日：1998-04-28
申请号：US836175
申请日：1997-04-17
IPC分类号： H01L21/8234 , H01L21/8246 , H01L27/088 , H01L27/112 , H01L29/739 , H01L29/78
CPC分类号： H01L27/112
摘要： A method for production of a read-only-memory cell arrangement having vertical MOS transistors is provided. In order to produce a read-only-memory cell arrangement which has first memory cells having a vertical MOS transistor and second memory cells which do not have a vertical MOS transistor, holes provided with a gate dielectric and a gate electrode are etched in a silicon substrate with a layer sequencing corresponding to a source, a channel and a drain for the first memory cells. Insulation trenches whose separation is preferably equal to their width are produced for insulation of adjacent memory cells.
摘要翻译： PCT No.PCT / DE95 / 01365 Sec。 371日期1997年04月17日 102（e）日期1997年4月17日PCT提交1995年10月5日PCT公布。 出版物WO96 / 13064 日期：1996年5月2日提供具有垂直MOS晶体管的只读存储单元布置方法。 为了产生具有垂直MOS晶体管的第一存储单元和不具有垂直MOS晶体管的第二存储单元的只读存储单元布置，在栅极电介质和栅电极中设置的孔被蚀刻在硅 具有对应于第一存储器单元的源极，沟道和漏极的层序列的衬底。 为了绝缘相邻的存储单元而产生绝缘沟槽，其隔离优选等于其宽度。
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公开(公告)号：US06518628B1
公开(公告)日：2003-02-11
申请号：US09423864
申请日：1999-11-15
IPC分类号： H01L2976
CPC分类号： H01L27/0922
摘要： An integrated CMOS circuit arrangement and a method of manufacturing same, which includes both a first MOS transistor and a second MOS transistor complementary thereto, wherein one of the MOS transistors is arranged at the floor of a trench and the other is arranged at the principal surface of a semiconductor substrate. The MOS transistors are arranged relative to one another such that a current flow through the MOS transistors respectively occurs substantially parallel to a sidewall of the trench that is arranged between the MOS transistors.
摘要翻译： 一种集成CMOS电路装置及其制造方法，其包括第一MOS晶体管和与其互补的第二MOS晶体管，其中MOS晶体管中的一个布置在沟槽的底部，而另一个布置在主表面 的半导体衬底。 MOS晶体管相对于彼此布置，使得流过MOS晶体管的电流分别基本上平行于布置在MOS晶体管之间的沟槽的侧壁。
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公开(公告)号：US5998261A
公开(公告)日：1999-12-07
申请号：US973701
申请日：1997-12-08
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L27/11517 , H01L27/115
摘要： An electrically writable and erasable read-only memory cell arrangement fabricated in a semiconductor substrate, preferably of monocrystalline silicon, or in a silicon layer of an SOI substrate. A cell array with memory cells is provided on a main surface of the semiconductor substrate. Each memory cell comprises an MOS transistor, vertical to the main surface and comprising, in addition to the source/drain region and a channel region arranged in-between, a first dielectric, a floating gate, a second dielectric and a control gate. A plurality of essentially parallel strip-shaped trenches are provided in the cell array. The vertical MOS transistors are arranged on the flanks of the trenches. The memory cells are in each case arranged on opposite flanks of the trenches.
摘要翻译： PCT No.PCT / DE96 / 01117 Sec。 371 1997年12月8日第 102（e）日期1997年12月8日PCT提交1996年6月25日PCT公布。 第WO97 / 02599号公报 日期1997年1月23日在半导体衬底（优选单晶硅）或SOI衬底的硅层中制造的电可写和可擦除的只读存储单元布置。 具有存储单元的单元阵列设置在半导体基板的主表面上。 每个存储单元包括垂直于主表面的MOS晶体管，并且除了源极/漏极区域和布置在其之间的沟道区域之外还包括第一电介质，浮动栅极，第二电介质和控制栅极。 多个基本上平行的带状沟槽设置在单元阵列中。 垂直MOS晶体管布置在沟槽的侧面。 存储单元在每种情况下都布置在沟槽的相对侧面上。
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公开(公告)号：US5920099A
公开(公告)日：1999-07-06
申请号：US913332
申请日：1997-09-11
IPC分类号： H01L21/8246 , H01L27/112
CPC分类号： H01L27/1126 , H01L27/112
摘要： A read-only memory cell array has a plurality of individual memory cells which each have a MOS transistor and which are arranged in rows running in parallel. In this context, adjacent rows run alternately at the bottom of the longitudinal trenches (6) and between adjacent longitudinal trenches (6) respectively and are insulated with respect to one another. The read-only memory cell array can be manufactured by self-aligning process steps with an area of 2 F.sup.2 (F: minimum structure size) being required per memory cell.
摘要翻译： PCT No.PCT / DE96 / 00380 Sec。 371日期：1997年9月11日 102（e）1997年9月11日PCT PCT 1996年3月4日PCT公布。 公开号WO96 / 29739 日期1996年9月26日只读存储单元阵列具有多个单独的存储单元，每个单独存储单元具有MOS晶体管并且并行排列。 在这种情况下，相邻的行分别在纵向沟槽（6）的底部和相邻的纵向沟槽（6）之间交替地延伸并相对于彼此绝缘。 只读存储单元阵列可以通过每个存储单元需要2 F2（F：最小结构尺寸）面积的自对准工艺步骤来制造。
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