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公开(公告)号：US08359445B2
公开(公告)日：2013-01-22
申请号：US12360780
申请日：2009-01-27
IPC分类号： G06F13/36
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A method and apparatus for signaling between devices of a memory system is provided. In accordance with an embodiment of the invention, one or more of several capabilities are implemented to provide heretofore unattainable levels of important system metrics, for example, high performance and/or low cost. These capabilities relate to timing adjustment capabilities, bit time adjustment capabilities, cycle time selection, use of differential and/or non-differential signaling for bus signals and/or clock signals, use of termination structures on a bus, including integrated termination structures, and active control circuitry to allow adjustment to different characteristic bus impedances and power-state control, including a calibration process to optimize the termination value, use of slew rate control circuitry and transfer characteristic control circuitry in the predriver and driver of transmitter blocks to allow adjustment to different characteristic bus impedances and to allow adjustment for other bus properties, including a calibration process to optimize the such circuitry, and/or provision of a memory component designed to prefetch (preaccess) words that are wider than the width of the data bus so that the memory access bandwidth approximately matches the transfer bandwidth, and memory component able to adjust the size of the prefetch (preaccess) word to accommodate connection to data buses of different width.
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公开(公告)号：US08165187B2
公开(公告)日：2012-04-24
申请号：US12173530
申请日：2008-07-15
CPC分类号： H04B17/11 , H04B17/00 , H04B17/21 , H04L7/0004 , H04L7/0016 , H04L7/0087 , H04L7/043 , H04L7/10 , H04L27/00
摘要： A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.
摘要翻译： 提供执行第一校准序列的方法和系统，例如在系统初始化时，建立操作值，其利用旨在穷举的算法，并且不时地执行第二校准序列以测量 在参数中漂移，并根据测量的漂移更新操作值。 与第一校准序列相比，第二校准序列使用较少的通信信道资源。 在一个实施例中，用于操作值的测量和收敛的第一校准序列利用长校准模式，例如大于30字节的代码，或长度为2N-1位的伪随机比特序列，其中N等于或大于 而第二校准序列使用短校准模式，例如小于16字节的固定代码，例如短至2字节长。
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13.发明授权Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules 有权增加具有不匹配内存模块的每个模块内存系统带宽的技术公开(公告)号：US06961831B2
公开(公告)日：2005-11-01
申请号：US10862375
申请日：2004-06-08
CPC分类号： G06F13/1684 , G11C8/16
摘要： Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one particular exemplary embodiment, the techniques may be realized through a memory system comprising a memory module and a memory controller. The memory module comprises a memory component with a memory core for storing data therein. The memory controller comprises a first set of interface connections that provides access to the memory module, a second set of interface connections that provides access to the memory module, and memory access circuitry that provides memory access signals to the memoory module for selecting between a first mode wherein first and second portions of the memory core are accessible through the first and second sets of interface connections, respectively, and a second mode wherein both the first and second pertions of the memory core are accessible through the first set of interface connections.
摘要翻译： 公开了用于增加具有不匹配的存储器模块的每模块模块存储器系统中的带宽的技术。 在一个特定的示例性实施例中，可以通过包括存储器模块和存储器控制器的存储器系统实现这些技术。 存储器模块包括具有用于在其中存储数据的存储器核心的存储器组件。 存储器控制器包括提供对存储器模块的访问的第一组接口连接，提供对存储器模块的访问的第二组接口连接以及提供存储器访问信号到存储器模块的存储器访问电路，用于在第一 模式，其中存储器核心的第一和第二部分分别通过第一和第二组接口连接可访问;以及第二模式，其中存储器核心的第一和第二密码都可通过第一组接口连接访问。
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14.发明授权Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules 有权增加具有不匹配内存模块的每个模块内存系统带宽的技术公开(公告)号：US06785782B1
公开(公告)日：2004-08-31
申请号：US09948905
申请日：2001-09-10
IPC分类号： G06F1200
CPC分类号： G11C7/1048 , G11C5/04 , G11C5/066 , G11C7/1012
摘要： Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one exemplary embodiment, the techniques are realized through a memory module for storing data thereon. The memory module comprises a memory component having a first set of interface connections for providing access to a memory core of the memory component and a second set of interface connections for providing access to the memory core of the memory component. The memory module also comprises memory access circuitry for selecting between a first mode wherein a first portion of the memory core is accessible through the first set of interface connections and a second portion of the memory core is accessible through the second set of interface connections, and a second mode wherein both the first portion and the second portion of the memory core are accessible through the first set of interface connections.
摘要翻译： 公开了用于增加具有不匹配的存储器模块的每模块模块存储器系统中的带宽的技术。 在一个示例性实施例中，通过用于在其上存储数据的存储器模块实现这些技术。 存储器模块包括具有用于提供对存储器组件的存储器核心的访问的第一组接口连接的存储器组件和用于提供对存储器组件的存储器核心的访问的第二组接口连接。 存储器模块还包括用于在第一模式之间进行选择的存储器访问电路，其中存储器核心的第一部分可通过第一组接口连接访问，并且存储器核心的第二部分可通过第二组接口连接访问，以及 第二模式，其中存储器核心的第一部分和第二部分都可通过第一组接口连接访问。
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公开(公告)号：US08462566B2
公开(公告)日：2013-06-11
申请号：US12111816
申请日：2008-04-29
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A memory component having a first and second interface. The first interface is provided to sample address information in response to a first clock signal. The first interface includes inputs to sample at least two bits of the address information in succession during a clock cycle of the first clock signal. The second interface is provided to sample data in response to a second clock signal, having a frequency that is at least twice the frequency of the first clock signal. The second interface includes inputs to sample at least two bits of data in succession during a clock cycle of the second clock signal.
摘要翻译： 一种具有第一和第二接口的存储器组件。 提供第一接口以响应于第一时钟信号对地址信息进行采样。 第一接口包括在第一时钟信号的时钟周期期间连续地采样地址信息的至少两个比特的输入。 提供第二接口以响应于第二时钟信号采样数据，其具有至少是第一时钟信号频率的两倍的频率。 第二接口包括在第二时钟信号的时钟周期期间连续采样至少两位数据的输入。
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公开(公告)号：US08391039B2
公开(公告)日：2013-03-05
申请号：US11280560
申请日：2005-11-15
IPC分类号： G11C5/02
CPC分类号： G11C7/1039 , G11C5/04 , G11C5/063 , G11C7/1048
摘要： A module having first and second memory devices and a termination component. A first signal line is coupled to the first memory device to provide first data thereto, the first data to be stored in a memory array of the first memory device during a write operation. A second signal line is coupled to the second memory device to provide thereto, the second data to be stored in a memory array of the second memory device during the write operation. A control signal path is coupled to the first memory device, the second memory device and the termination component such that a write command propagating on the control signal path propagates past the first memory device and the second memory device before reaching the first termination component, wherein the write command specifies the write operation.
摘要翻译： 具有第一和第二存储器件和终端部件的模块。 第一信号线耦合到第一存储器件，以在写入操作期间向第一存储器件提供第一数据以存储在第一存储器件的存储器阵列中。 第二信号线耦合到第二存储器设备以在写入操作期间提供要存储在第二存储器件的存储器阵列中的第二数据。 控制信号路径被耦合到第一存储器件，第二存储器件和终端元件，使得在到达第一端接元件之前，在控制信号路径上传播的写入命令经过第一存储器件和第二存储器件传播，其中 write命令指定写入操作。
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公开(公告)号：US08380927B2
公开(公告)日：2013-02-19
申请号：US12538613
申请日：2009-08-10
CPC分类号： G06F13/409 , G11C5/04 , G11C2207/105 , H05K1/117 , H05K1/14 , H05K2201/09954 , H05K2201/10189 , Y02D10/14 , Y02D10/151
摘要： Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filter elements, thereby allowing the termination characteristics to be tuned for different levels of speed performance and power consumption. Termination voltages and impedances might also be adjusted.
摘要翻译： 描述的是采用可配置的片上终端元件的系统，其允许用户从两个或多个端接拓扑中进行选择。 一个拓扑结构可编程，以支持轨到轨或半电源终端。 另一种拓扑选择性地包括固定或可变滤波器元件，从而允许针对不同级别的速度性能和功耗来调整终端特性。 终端电压和阻抗也可能会被调整。
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公开(公告)号：US20120287725A1
公开(公告)日：2012-11-15
申请号：US13543779
申请日：2012-07-06
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A DRAM controller component generates a timing signal and transmits, to a DRAM, (i) write data that requires a first time interval to propagate from the DRAM controller component to the DRAM and to be sampled by the DRAM on one or more edges of the timing signal, (ii) a clock signal that requires a second time interval to propagate from the DRAM controller component to the DRAM, and (iii) a write command, associated with the write data, to be sampled by the DRAM on one or more edges of the clock signal. The DRAM controller component includes series-coupled delay elements to generate respective incrementally delayed signals, and a multiplexer to select one of the delayed signals to time the transmission of the write data, such that transmission of the write data is delayed based on a difference between the first time interval and the second time interval.
摘要翻译： DRAM控制器组件产生定时信号并向DRAM发送（i）写入需要第一时间间隔的数据，以从DRAM控制器组件传播到DRAM，并在DRAM的一个或多个边缘上对DRAM进行采样 定时信号，（ii）需要第二时间间隔从DRAM控制器组件传播到DRAM的时钟信号，以及（iii）与写入数据相关联的写入命令，以由DRAM在一个或多个 时钟信号的边沿。 DRAM控制器组件包括串联耦合的延迟元件以产生相应的递增延迟的信号，以及多路复用器，用于选择延迟信号中的一个来对写入数据进行传输，以便写入数据的传输基于 第一时间间隔和第二时间间隔。
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公开(公告)号：US20120213020A1
公开(公告)日：2012-08-23
申请号：US13461923
申请日：2012-05-02
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A memory component having a first and second interface. The first interface is provided to sample address information in response to a first clock signal. The first interface includes inputs to sample at least two bits of the address information in succession during a clock cycle of the first clock signal. The second interface is provided to sample data in response to a second clock signal, having a frequency that is at least twice the frequency of the first clock signal. The second interface includes inputs to sample at least two bits of data in succession during a clock cycle of the second clock signal.
摘要翻译： 一种具有第一和第二接口的存储器组件。 提供第一接口以响应于第一时钟信号对地址信息进行采样。 第一接口包括在第一时钟信号的时钟周期期间连续地采样地址信息的至少两个比特的输入。 提供第二接口以响应于第二时钟信号采样数据，其具有至少是第一时钟信号频率的两倍的频率。 第二接口包括在第二时钟信号的时钟周期期间连续采样至少两位数据的输入。
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公开(公告)号：US07610447B2
公开(公告)日：2009-10-27
申请号：US09797099
申请日：2001-02-28
CPC分类号： G06F13/409 , G11C5/04 , G11C2207/105 , H05K1/117 , H05K1/14 , H05K2201/09954 , H05K2201/10189 , Y02D10/14 , Y02D10/151
摘要： Described herein is a point-to-point memory communications architecture, having a point-to-point signal line set associated with each of a plurality of connectors or module positions. When the system is fully populated, there is a one-to-one correspondence between signal line sets and memory modules. In systems that are not fully populated, the system is configurable to use a plurality of the signal line sets for a single memory module.
摘要翻译： 这里描述的是具有与多个连接器或模块位置中的每一个相关联的点对点信号线集合的点对点存储器通信架构。 当系统完全填充时，信号线组和存储器模块之间存在一一对应关系。 在未完全填充的系统中，系统可配置为对于单个存储器模块使用多个信号线组。
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