公开(公告)号：US06284599B1

公开(公告)日：2001-09-04

申请号：US09585059

申请日：2000-06-01

申请人： Freidoon Mehrad ,  George R. Misium ,  John H. MacPeak

发明人： Freidoon Mehrad ,  George R. Misium ,  John H. MacPeak

IPC分类号： H01L21336

CPC分类号： H01L27/115 ,  H01L27/0629 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L28/20

摘要： A method for fabricating a semiconductor resistor in embedded FLASH memory applications is described. In the method a gate stack (54) is formed on an insulating region (70) of a semiconductor substrate. The control gate (20) is removed from the gate stack (54) and electric contacts (125), (130) are formed to contact the floating gate (16) to form the resistor.

摘要翻译： 描述了在嵌入式FLASH存储器应用中制造半导体电阻器的方法。 在该方法中，在半导体衬底的绝缘区域（70）上形成栅叠层（54）。 控制栅极（20）从栅极堆叠（54）移除，并且电触点（125），（130）形成为接触浮动栅极（16）以形成电阻器。

公开(公告)号：US6087220A

公开(公告)日：2000-07-11

申请号：US124798

申请日：1998-07-29

申请人： Daty Michael Rogers ,  Reima T. Laaksonen ,  Cetin Kaya ,  Freidoon Mehrad ,  Men-Chee Chen

发明人： Daty Michael Rogers ,  Reima T. Laaksonen ,  Cetin Kaya ,  Freidoon Mehrad ,  Men-Chee Chen

IPC分类号： H01L21/28 ,  H01L21/336

CPC分类号： H01L21/28273

摘要： A method of forming a floating gate memory array is provided that uses a two step etch process to prevent the formation of unwanted trenches 66 into the semiconductor substrate 26. The process may be accomplished by a first etch which is substantially not selective between silicon and dielectric materials. A second etch process is then used which is highly selective to dielectric materials.

摘要翻译： 提供了形成浮栅存储器阵列的方法，其使用两步蚀刻工艺来防止在半导体衬底26中形成不需要的沟槽66.该工艺可以通过在硅和电介质之间基本上不选择性的第一蚀刻来实现 材料 然后使用对介电材料具有高度选择性的第二蚀刻工艺。

公开(公告)号：US6071779A

公开(公告)日：2000-06-06

申请号：US225436

申请日：1999-01-05

申请人： Freidoon Mehrad ,  Sarma S. Gunturi ,  Cetin Kaya ,  Kyle A. Picone

发明人： Freidoon Mehrad ,  Sarma S. Gunturi ,  Cetin Kaya ,  Kyle A. Picone

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521

摘要： A method of fabricating a semiconductor device having a memory array (9) that includes a source line (24) is provided. The method of forming the source line (24) may include providing a semiconductor substrate (52) having a source region (60) separated from a drain region (62) by a channel region (64). An isolation structure (70) may be formed in the semiconductor substrate (52). The isolation structure (70) may cross the source region (60), the drain region (62), and the channel region (64) of the semiconductor substrate (52). An isolation dielectric material (78) may be formed within the isolation structure (70). A continuous stack structure (50) may be formed outwardly from the channel region (64) of the semiconductor substrate (52) and the isolation structure (70). A first photomask (100) may be formed outwardly from the continuous stack structure (50) and the semiconductor substrate (52). The first photomask (100) may expose a strip region (102) of the semiconductor substrate (52) and the isolation structure (70). The isolation dielectric material (78) may be removed from the exposed portion the isolation structure (70) to expose the semiconductor substrate (52). A dopant may be implanted into the exposed semiconductor substrate (52) to form the source line (24) in the semiconductor device.

摘要翻译： 提供一种制造具有包括源极线（24）的存储器阵列（9）的半导体器件的方法。 形成源极线（24）的方法可以包括提供具有通过沟道区（64）与漏极区（62）分离的源极区（60）的半导体衬底（52）。 隔离结构（70）可以形成在半导体衬底（52）中。 隔离结构（70）可以穿过半导体衬底（52）的源极区域（60），漏极区域（62）和沟道区域（64）。 隔离电介质材料（78）可以形成在隔离结构（70）内。 可以从半导体衬底（52）的沟道区（64）和隔离结构（70）向外形成连续堆叠结构（50）。 可以从连续堆叠结构（50）和半导体衬底（52）向外形成第一光掩模（100）。 第一光掩模（100）可以暴露半导体衬底（52）和隔离结构（70）的条带区域（102）。 隔离电介质材料（78）可以从隔离结构（70）的暴露部分去除以暴露半导体衬底（52）。 可以将掺杂剂注入到暴露的半导体衬底（52）中以在半导体器件中形成源极线（24）。

公开(公告)号：US5576992A

公开(公告)日：1996-11-19

申请号：US521555

申请日：1995-08-30

申请人： Freidoon Mehrad

发明人： Freidoon Mehrad

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/34 ,  G11C16/00

CPC分类号： G11C16/3409 ,  G11C16/3404

摘要： An extended-life method for soft-programming at least one floating gate memory cell (10) includes connecting the substrate and the source (11) to a reference voltage, then applying to the control gate (13) a soft-programming voltage, the soft-programming voltage being between thirty and sixty percent of the voltage used to hard-program the cell. Increasing voltages are applied to the drain (12), while measuring the current flow into the drain (12). A specific drain (12) voltage, less than or equal to that value of drain (12) voltage at which the current flow into the drain (12) reaches a first peak, is chosen. With the substrate at reference voltage, the cell (10) is soft-programmed by applying to the drain (12) a first voltage slightly less than or equal to the specific drain (12) voltage; by applying to the source (11) a non-negative second voltage less than the specific drain (12) voltage; and by applying to the control gate (13) a third voltage no greater than the soft-programming voltage.

摘要翻译： 用于软编程至少一个浮动栅极存储单元（10）的延长寿命方法包括将衬底和源极（11）连接到参考电压，然后向控制栅极（13）施加软编程电压， 软编程电压是用于硬编程单元的电压的三十到百分之六十。 在测量进入漏极（12）的电流的同时，向漏极（12）施加增加的电压。 选择小于或等于流入漏极（12）的电流的漏极（12）电压达到第一峰值的特定漏极（12）电压。 在衬底处于参考电压的情况下，电池（10）通过向漏极（12）施加稍微小于或等于特定漏极（12）电压的第一电压而进行软编程; 通过向源极（11）施加小于特定漏极（12）电压的非负第二电压; 并且通过向控制栅极（13）施加不大于软编程电压的第三电压。

公开(公告)号：US08273645B2

公开(公告)日：2012-09-25

申请号：US12537336

申请日：2009-08-07

申请人： Mark Robert Visokay ,  Freidoon Mehrad ,  Richard L. Guldi ,  Yaw Samuel Obeng

发明人： Mark Robert Visokay ,  Freidoon Mehrad ,  Richard L. Guldi ,  Yaw Samuel Obeng

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/28097 ,  H01L21/823835 ,  H01L29/4975 ,  H01L29/66507 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming fully silicided (FUSI) gates in MOS transistors which is compatible with wet etch processes used in source/drain silicide formation is disclosed. The gate silicide formation step produces a top layer of metal rich silicide which is resistant to removal in wet etch processes. A blocking layer over active areas prevents source/drain silicide formation during gate silicide formation. Wet etches during removal of the blocking layer and source/drain metal strip do not remove the metal rich gate silicide layer. Anneal of the gate silicide to produce a FUSI gate with a desired stoichiometry is delayed until after formation of the source/drain silicide. The disclosed method is compatible with nickel and nickel-platinum silicide processes.

摘要翻译： 公开了一种在MOS晶体管中形成完全硅化（FUSI）栅极的方法，其与源极/漏极硅化物形成中使用的湿蚀刻工艺兼容。 栅极硅化物形成步骤产生富含金属的硅化物的顶层，其耐湿蚀刻工艺中的去除。 有源区域上的阻挡层防止栅极硅化物形成期间的源/漏硅化物形成。 去除阻挡层和源极/漏极金属带期间的湿蚀刻不能去除富金属栅极硅化物层。 栅极硅化物的退火以产生具有所需化学计量的FUSI栅极被延迟直到形成源极/漏极硅化物。 所公开的方法与镍和镍 - 铂硅化物工艺兼容。

公开(公告)号：US20100176462A1

公开(公告)日：2010-07-15

申请号：US12731932

申请日：2010-03-25

申请人： Freidoon Mehrad ,  Shaofeng Yu ,  Steven A. Vitale ,  Joe G. Tran

发明人： Freidoon Mehrad ,  Shaofeng Yu ,  Steven A. Vitale ,  Joe G. Tran

IPC分类号： H01L29/78

CPC分类号： H01L29/665 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/4975 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.

摘要翻译： 同时硅化半导体器件的多晶硅栅极和源极/漏极的方法以及相关器件。 示例性实施例中的至少一些是包括在半导体衬底上形成栅极堆叠的方法（栅堆叠包括第一多晶硅层，第一氮化物层和第二多晶硅层），在有源区上形成第二氮化物层 所述半导体衬底与所述栅极堆叠相邻，执行停止在所述第一氮化物层和所述第二氮化物层上的化学机械抛光，去除所述第一氮化物层和所述第二氮化物层，以及执行所述第一多晶硅层的同时硅化;以及 活跃区域。

公开(公告)号：US07727842B2

公开(公告)日：2010-06-01

申请号：US11741519

申请日：2007-04-27

申请人： Freidoon Mehrad ,  Shaofeng Yu ,  Steven A. Vitale ,  Joe G. Tran

发明人： Freidoon Mehrad ,  Shaofeng Yu ,  Steven A. Vitale ,  Joe G. Tran

IPC分类号： H01L21/8234

CPC分类号： H01L29/665 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/4975 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.

摘要翻译： 同时硅化半导体器件的多晶硅栅极和源极/漏极的方法以及相关器件。 示例性实施例中的至少一些是包括在半导体衬底上形成栅极堆叠的方法（栅堆叠包括第一多晶硅层，第一氮化物层和第二多晶硅层），在有源区上形成第二氮化物层 所述半导体衬底与所述栅极堆叠相邻，执行停止在所述第一氮化物层和所述第二氮化物层上的化学机械抛光，去除所述第一氮化物层和所述第二氮化物层，以及执行所述第一多晶硅层的同时硅化;以及 活跃区域。

公开(公告)号：US07396716B2

公开(公告)日：2008-07-08

申请号：US11201924

申请日：2005-08-11

申请人： Freidoon Mehrad ,  Shaofeng Yu ,  Joe G. Tran

发明人： Freidoon Mehrad ,  Shaofeng Yu ,  Joe G. Tran

IPC分类号： H01L21/311

CPC分类号： H01L21/823425 ,  H01L21/28097 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/823443 ,  H01L21/823468 ,  H01L21/823835 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a capping layer 610 over gate structures 230 located over a microelectronics substrate 210 wherein the gate structures 230 include sidewall spacers 515 and have a doped region 525 located between them. A protective layer 710 is placed over the capping layer 610 and the doped region 525, and a portion of the protective layer 710 and capping layer 610 that are located over the gate structures are removed to expose a top surface of the gate structures 230. A remaining portion of the protective layer 710 and capping layer 610 remains over the doped region 525. With the top surface of the gate structures 230 exposed, metal is incorporated into the gate structures to form gate electrodes 230.

摘要翻译： 本发明提供一种制造微电子器件的方法。 在一个方面，该方法包括在位于微电子器件衬底210之上的栅极结构230上形成覆盖层610，其中栅极结构230包括侧壁间隔物515并且具有位于它们之间的掺杂区域525。 保护层710放置在覆盖层610和掺杂区域525之上，并且去除位于栅极结构上方的保护层710和覆盖层610的一部分以露出栅极结构230的顶表面。 保护层710和覆盖层610的剩余部分保留在掺杂区域525之上。 在栅极结构230的顶表面暴露的情况下，将金属结合到栅极结构中以形成栅电极230。

公开(公告)号：US20050208732A1

公开(公告)日：2005-09-22

申请号：US11142483

申请日：2005-06-01

申请人： Zhihao Chen ,  Freidoon Mehrad ,  Brian Kirkpatrick ,  Jeff White ,  Edmund Russell ,  Jon Holt ,  Jason Mehigan

发明人： Zhihao Chen ,  Freidoon Mehrad ,  Brian Kirkpatrick ,  Jeff White ,  Edmund Russell ,  Jon Holt ,  Jason Mehigan

IPC分类号： H01L21/316 ,  H01L21/762 ,  H01L21/76 ,  H01L21/302 ,  H01L21/311 ,  H01L21/461

CPC分类号： H01L21/02126 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L21/76235

摘要： A trench structure in a wafer of semiconductor material and the method of forming the trench structure are described. The trench structure is formed on a semiconductor wafer that has a top surface of slow oxidization rate—slower than that of other major crystallographic planes of the semiconductor material. The trench is etched into the semiconductor wafer. The trench has substantially vertical trench-sidewalls near the top surface, the vertical trench-sidewalls near the top surface containing crystallographic plane that oxidizes at a rate comparable to that of the top surface. An insulating layer is grown on the top surface and on the trench-sidewalls and on corners where sidewall surfaces approach the top surface, the insulating layer at the corners being substantially thicker than at the sidewall adjacent to the corners. The difference in the oxide thickness is due to the faster oxidizing planes exposed at the corners. Finally, the trench is filled with a dielectric material.

公开(公告)号：US20050101101A1

公开(公告)日：2005-05-12

申请号：US10703387

申请日：2003-11-06

申请人： Juanita DeLoach ,  Freidoon Mehrad ,  Brian Trentman ,  Troy Yocum

发明人： Juanita DeLoach ,  Freidoon Mehrad ,  Brian Trentman ,  Troy Yocum

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232

摘要： In one embodiment, a method for forming a semiconductor structure in manufacturing a semiconductor device includes providing a pad layer on a surface of a substrate, providing a nitride layer on the pad layer, and providing a sacrificial oxide layer on the nitride layer. In a first etching step, at least the sacrificial oxide and nitride layers are etched to define opposing substantially vertical surfaces of at least the sacrificial oxide and nitride layers. In a second etching step, the nitride layer is etched such that the opposing substantially vertical surfaces of the nitride layer are recessed from the opposing substantially vertical surfaces of the sacrificial oxide layer, the sacrificial oxide layer substantially preventing the nitride layer from decreasing in thickness as a result of the etching of the nitride layer. In a third etching step, the substrate is etched to form a trench extending into the substrate for purposes of defining one or more isolation regions adjacent the trench.

摘要翻译： 在一个实施例中，在制造半导体器件中形成半导体结构的方法包括在衬底的表面上提供焊盘层，在焊盘层上提供氮化物层，并在氮化物层上提供牺牲氧化物层。 在第一蚀刻步骤中，至少牺牲氧化物层和氮化物层被蚀刻以限定至少牺牲氧化物层和氮化物层的相对的基本垂直的表面。 在第二蚀刻步骤中，蚀刻氮化物层，使得氮化物层的相对的基本上垂直的表面从牺牲氧化物层的相对的基本上垂直的表面凹陷，牺牲氧化物层基本上防止氮化物层的厚度减小 蚀刻氮化物层的结果。 在第三蚀刻步骤中，蚀刻衬底以形成延伸到衬底中的沟槽，用于限定与沟槽相邻的一个或多个隔离区域。