公开(公告)号：US20060195287A1

公开(公告)日：2006-08-31

申请号：US11055829

申请日：2005-02-11

申请人： Ulrich Weiss

发明人： Ulrich Weiss

IPC分类号： G01R27/28

CPC分类号： G01R31/2853 ,  G01R31/31717

摘要： A method, apparatus, and computer program product in a data processing system for testing differential clock or oscillator signals. A method is comprised of the following steps: A first single-ended receiver is connected to a positive leg of a differential pair, and a second single-ended receiver is connected to a negative leg of the differential pair. An output of the first single-ended receiver is inverted and delayed before being input into a first RS Flip-Flop. An output of the second single-ended receiver is delayed before being input into a second RS Flip-Flop. An output of a differential receiver is inverted and input into the first and second RS Flip Flops as reset signals. Then a Wire OK signal is output indicating the condition of the legs of the differential pair.

摘要翻译： 用于测试差分时钟或振荡器信号的数据处理系统中的方法，装置和计算机程序产品。 一种方法包括以下步骤：第一单端接收器连接到差分对的正极，而第二单端接收器连接到差分对的负极。 在输入到第一RS触发器之前，第一单端接收器的输出被反相和延迟。 第二单端接收器的输出在被输入到第二RS触发器之前被延迟。 差分接收器的输出被反相并作为复位信号输入到第一和第二RS触发器。 然后输出一条Wire OK信号，指示差动对的支脚状态。

公开(公告)号：US20060184814A1

公开(公告)日：2006-08-17

申请号：US11056009

申请日：2005-02-11

申请人： Dietmar Schmunkamp ,  Andreas Wagner ,  Tobias Webel ,  Ulrich Weiss

发明人： Dietmar Schmunkamp ,  Andreas Wagner ,  Tobias Webel ,  Ulrich Weiss

IPC分类号： G06F1/06

CPC分类号： G06F11/1604 ,  G06F11/20

摘要： The present invention relates to system clocking in computer systems. In particular, it relates to system clocking in high-end multi-processor, multi-node server computer systems with an enhanced degree of performance and reliability and to a method for dynamically switching between a first and a second clock signal, if the first should fail. More redundancy even to the Dynamic Clock Switching Circuit (DCSC) (14) and the wiring (17) from there to multiple, PLL-(12) free clock chips (22) is provided. Instead of only one DCSC (14) and one single wiring (17), two of them (14-0, 14-1; 17-0, 17-1) are used combined with a further particular logic present on each clock chip (22), which in combination generate two synchronous, fine-tuned, minimum-shifted clock signals and select always the first of them to arrive at a FlipFlop controlling the output for clock distribution wiring.

摘要翻译： 本发明涉及计算机系统中的系统时钟。 特别地，它涉及具有增强的性能和可靠性程度的高端多处理器，多节点服务器计算机系统中的系统时钟以及用于在第一和第二时钟信号之间动态切换的方法，如果第一应用 失败。 提供了更多的冗余，即使是动态时钟切换电路（DCSC）（14）和布线（17），也可以是多个PLL-（12）空闲时钟芯片（22）。 而不是只有一个DCSC（14）和一个单个布线（17），它们中的两个（14 - 0，14 - 1，17 - 0，17 - 1）与每个时钟芯片上存在的另一个特定逻辑 22），其组合产生两个同步，微调的最小移位时钟信号，并总是选择第一个来获得控制时钟分配布线输出的FlipFlop。

公开(公告)号：US5306959A

公开(公告)日：1994-04-26

申请号：US858252

申请日：1992-03-26

申请人： Guenter Knauft ,  Bernd Leppla ,  Dietmar Schmunkamp ,  Ulrich Weiss

发明人： Guenter Knauft ,  Bernd Leppla ,  Dietmar Schmunkamp ,  Ulrich Weiss

IPC分类号： H03K5/15 ,  H03K5/04 ,  H03K3/284 ,  H03K5/13 ,  H03K7/00

CPC分类号： H03K5/15

摘要： An electrical circuit for generating clock pulses for a multi-chip computer system which contains a clock generation chip and various logic circuit chips. The clock pulses used on the logic circuit chips are generated on the clock generation chip and are transferred to the logic circuit chips. For the generation of the clock pulses a so-called clock splitter circuit is provided on the clock generation circuit. This clock splitter generates two pulse strings out of a third pulse string which is derived from an oscillator. The clock splitter contains a number of gates and latches which have an impact on the throughput time of a pulse to run through the clock splitter, as well as on the skew of the two generated pulse strings. The invention provides an electrical circuit which has an improved throughput time and skew of the generated pulse strings.

摘要翻译： 一种用于为包含时钟生成芯片和各种逻辑电路芯片的多芯片计算机系统产生时钟脉冲的电路。 逻辑电路芯片上使用的时钟脉冲在时钟产生芯片上产生并被传送到逻辑电路芯片。 为了产生时钟脉冲，在时钟产生电路上提供所谓的时钟分配器电路。 该时钟分配器产生从振荡器导出的第三脉冲串中的两个脉冲串。 时钟分配器包含多个门和锁存器，这些门和锁存器对脉冲通过时钟分配器的吞吐量时间以及两个产生的脉冲串的偏斜有影响。 本发明提供了一种电路，其具有改善的生成时间和产生的脉冲串的偏斜。

公开(公告)号：US08086657B2

公开(公告)日：2011-12-27

申请号：US12099973

申请日：2008-04-09

申请人： Wilhelm Haller ,  Rolf Sautter ,  Christoph Wandel ,  Ulrich Weiss

发明人： Wilhelm Haller ,  Rolf Sautter ,  Christoph Wandel ,  Ulrich Weiss

IPC分类号： G06F7/50

CPC分类号： H03K19/0941 ,  H03K19/0008

摘要： A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input (60, 62) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.

摘要翻译： 一种数字加法器电路，包括在所述加法器电路的进位逻辑中的多个逻辑级，用于产生和传播预定的操作数位组，每个级实现预定的逻辑功能，并处理来自前一级的输入变量，并将结果值输出到 4位加法器的进位网络中的后级静态和动态逻辑，并且来自第一级的输出直接作为输入（60,62）馈送到进位网络的第三级。 优选地，具有通常相对较高切换活动的阶段在静态逻辑中实现。 优选地，其进位网络的第一级是以静态逻辑实现的，其余的级在动态逻辑中。

公开(公告)号：US07761726B2

公开(公告)日：2010-07-20

申请号：US12116652

申请日：2008-05-07

申请人： Scott Barnett Swaney ,  Kenneth Lundy Ward ,  Tobias Webel ,  Ulrich Weiss ,  Matthias Woehrle

发明人： Scott Barnett Swaney ,  Kenneth Lundy Ward ,  Tobias Webel ,  Ulrich Weiss ,  Matthias Woehrle

IPC分类号： G06F1/12

CPC分类号： G06F11/1604 ,  G06F1/14 ,  G06F11/20

摘要： Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.

摘要翻译： 冗余时钟（TOD）振荡器在主振荡器路径内对准本地逻辑振荡器，并用于创建独立的步进同步信号。 步骤检验器验证并提供选择信号，以根据标准识别哪个TOD振荡器工作。 独立的步进同步信号被传送到几个同级芯片。 本地步进和同步信号被延迟到TOD寄存器，与同步芯片中的TOD寄存器几乎同步。 可以使用从属振荡器路径来选择在同级芯片中产生的时间信号，由此主振荡器路径被取消选择。 主控制寄存器组可以用于使用主振荡器路径来配置几个芯片中的哪一个是主芯片。 所有剩余的芯片都是从芯片。 拓扑的所有段都是冗余的。 多个可能的替代拓扑中的一个在二次控制寄存器集中被定义。 命令和TOD值以预定义的时间增量边界在结构上传递，以建立，恢复或维持所有芯片之间的同步。

公开(公告)号：US07487377B2

公开(公告)日：2009-02-03

申请号：US11054294

申请日：2005-02-09

申请人： Scott Barnett Swaney ,  Kenneth Lundy Ward ,  Tobias Webel ,  Ulrich Weiss ,  Matthias Woehrle

发明人： Scott Barnett Swaney ,  Kenneth Lundy Ward ,  Tobias Webel ,  Ulrich Weiss ,  Matthias Woehrle

IPC分类号： G06F13/42

CPC分类号： G06F11/1604 ,  G06F1/14 ,  G06F11/20

摘要： Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.

摘要翻译： 冗余时钟（TOD）振荡器在主振荡器路径内对准本地逻辑振荡器，并用于创建独立的步进同步信号。 步骤检验器验证并提供选择信号，以根据标准识别哪个TOD振荡器工作。 独立的步进同步信号被传送到几个同级芯片。 本地步进和同步信号被延迟到TOD寄存器，与同步芯片中的TOD寄存器几乎同步。 可以使用从属振荡器路径来选择在同级芯片中产生的时间信号，由此主振荡器路径被取消选择。 主控制寄存器组可以用于使用主振荡器路径来配置几个芯片中的哪一个是主芯片。 所有剩余的芯片都是从芯片。 拓扑的所有段都是冗余的。 多个可能的替代拓扑中的一个在二次控制寄存器集中被定义。 命令和TOD值以预定义的时间增量边界在结构上传递，以建立，恢复或维持所有芯片之间的同步。

公开(公告)号：US07296610B2

公开(公告)日：2007-11-20

申请号：US10800544

申请日：2004-03-15

申请人： Matthew Zaluzec ,  David Cook ,  Ulrich Weiss ,  Maik Broda ,  Clemens Verpoort

发明人： Matthew Zaluzec ,  David Cook ,  Ulrich Weiss ,  Maik Broda ,  Clemens Verpoort

IPC分类号： B22D19/04 ,  B22D19/08

CPC分类号： B22D19/0009 ,  B22D19/0081 ,  B22D19/08 ,  C23C2/02 ,  C23C4/18 ,  C23C6/00 ,  F01L3/04 ,  F01L2101/00 ,  F01L2103/00 ,  Y10T29/49231 ,  Y10T29/49984

摘要： A method of manufacturing metallic components consisting of at least two different materials, one of them being an iron-based alloy and the other an aluminum-based alloy, and involving the steps of: depositing a metallic layer onto the body made from the iron-based alloy, said layer being an aluminum-based alloy, preferably based on Al—Si or Fe, placing the coated body in a casting mold and casting an aluminum-based alloy about the coated body. Prior to placing the body in the casting mold, the metallic layer of the body is sprayed and/or blasted with silicon powder and/or Borax (Na2B4O7—10H2O, hydrated sodium borate).

摘要翻译： 一种制造由至少两种不同材料组成的金属组件的方法，其中一种是铁基合金，另一种是铝基合金，包括以下步骤：将金属层沉积在由铁 - 所述层是铝基合金，优选基于Al-Si或Fe，将涂覆体放置在铸模中并且在涂覆体周围浇铸铝基合金。 在将本体放置在铸模中之前，用硅粉和/或硼砂（Na 2 B 4 O 4）喷射和/或喷射身体的金属层， N 2，水合硼酸钠）。

公开(公告)号：US20060179364A1

公开(公告)日：2006-08-10

申请号：US11054294

申请日：2005-02-09

申请人： Scott Swaney ,  Kenneth Ward ,  Tobias Webel ,  Ulrich Weiss ,  Matthias Woehrle

发明人： Scott Swaney ,  Kenneth Ward ,  Tobias Webel ,  Ulrich Weiss ,  Matthias Woehrle

IPC分类号： G06F11/00

CPC分类号： G06F11/1604 ,  G06F1/14 ,  G06F11/20

摘要： Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.

公开(公告)号：US06989696B2

公开(公告)日：2006-01-24

申请号：US10707066

申请日：2003-11-19

申请人： Rolf Hilgendorf ,  Jens Kuenzer ,  Cédric Lichtenau ,  Thomas Pflueger ,  Mathew I. Ringler ,  Gerard M. Salem ,  Peter A. Sandon ,  Dana J. Thygesen ,  Ulrich Weiss

发明人： Rolf Hilgendorf ,  Jens Kuenzer ,  Cédric Lichtenau ,  Thomas Pflueger ,  Mathew I. Ringler ,  Gerard M. Salem ,  Peter A. Sandon ,  Dana J. Thygesen ,  Ulrich Weiss

IPC分类号： H03L7/00

CPC分类号： H03L7/06

摘要： A synchronization system capable of simultaneously resetting frequency divide-by counters (124A, 124B) of multiple processors (A, B) to zero regardless of the divide-by frequency signal (Mclk/n signal (168A, 168B)) and regardless of the magnitude of the clock mesh delays experienced by the Mclk/n signals in the processors. The synchronization system includes a mesh delay circuit (176A, 176B) for each processor that simulates in the undivided signal (Mclk/1 signal (136A, 136B)) the clock mesh delay experienced by the Mclk/n signal in that processor so as to provide an Lclk signal (172A, 172B). A phase detector detects the phase offset between the Mclk/n signal and the Sysclk signal (112) and sends an asynchronous offset signal (194A, 194B) to a counter re-setter (196A, 196B) that resets the divide-by counter to zero based on the offset signal.

摘要翻译： 能够将多个处理器（A，B）的频率分频计数器（124A，124BB）同时复位的同步系统为零，而不管分频频率 信号（Mclk / n信号（168A，168B）），并且与处理器中的Mclk / n信号经历的时钟网格延迟的大小无关。 同步系统包括用于在未分割信号中模拟的每个处理器的网格延迟电路（176A，176BB）（Mclk / 1信号（136 < / SUB>，136 B））由该处理器中的Mclk / n信号经历的时钟网格延迟，以便提供Lclk信号（172 ，172 _{B ）。 相位检测器检测Mclk / n信号和Sysclk信号之间的相位偏移（112），并将异步偏移信号（194A，192B）发送到计数器 基于偏移信号将再分配计数器复位为零的重新设置器（196A，196BB）。}

公开(公告)号：US4150236A

公开(公告)日：1979-04-17

申请号：US817094

申请日：1977-07-19

申请人： Ulrich Weiss ,  Kenner C. Rice

发明人： Ulrich Weiss ,  Kenner C. Rice

IPC分类号： C07C51/00 ,  C07C62/38 ,  C07C67/00 ,  C07C69/757 ,  C07C69/94

CPC分类号： C07C62/38

摘要： Tricyclic aromatic compounds of the formula ##STR1## including those wherein: (A) R.sub.1 is H, R.sub.2 is carbomethoxy, and R.sub.3 is methyl;(b) R.sub.1 is acetyl, R.sub.2 is carbomethoxy, and R.sub.3 is methyl;(c) R.sub.1 and R.sub.3 are methyl and R.sub.2 is carbomethoxy;(d) R.sub.1, R.sub.2, and R.sub.3 are hydrogen; and(e) R.sub.1 and R.sub.3 are methyl and R.sub.2 is hydrogenAre intermediates for the total synthesis of steroids.