公开(公告)号：US10691463B2

公开(公告)日：2020-06-23

申请号：US15220067

申请日：2016-07-26

Applicant: Futurewei Technologies, Inc.

Inventor： Sushma Wokhlu ,  Alan Gatherer ,  Ashish Rai Shrivastava

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48

Abstract: A system and method for variable lane architecture includes memory blocks located in a memory bank, one or more computing nodes forming a vector instruction pipeline for executing a task, each of the computing nodes located in the memory bank, each of the computing nodes executing a portion of the task independently of other ones of the computing nodes, and a global program controller unit (GPCU) forming a scalar instruction pipeline for executing the task, the GPCU configured to schedule instructions for the task at one or more of the computing nodes, the GPCU further configured to dispatch an address for the memory blocks used by each of the computing nodes to the computing nodes.

公开(公告)号：US20180300258A1

公开(公告)日：2018-10-18

申请号：US15486699

申请日：2017-04-13

Applicant: Futurewei Technologies, Inc.

Inventor： Sushma Wokhlu ,  Alex Elisa Chandra ,  Alan Gatherer

IPC: G06F12/126

Abstract: A method of operating a cache memory comprises receiving a first read or write command including at least a first address referring to first data and a first rank indicator associated with the first data, and in response to receiving the first read or write command, reading or writing the first data referenced by the first address, and storing the first rank indicator.

公开(公告)号：US20170300414A1

公开(公告)日：2017-10-19

申请号：US15131779

申请日：2016-04-18

Applicant: Futurewei Technologies, Inc.

Inventor： Sushma Wokhlu ,  Alan Gatherer ,  Ashish Rai Shrivastava

IPC: G06F12/08

CPC classification number: G06F12/0893 ,  G06F12/0877

Abstract: A cache and a method for operating a cache are disclosed. In an embodiment, the cache includes a cache controller, data cache and a delay write through cache (DWTC), wherein the data cache is separate and distinct from the DWTC, wherein cacheable write accesses are split into shareable cacheable write accesses and non-shareable cacheable write accesses, wherein the cacheable shareable write accesses are allocated only to the DWTC, and wherein the non-shareable cacheable write accesses are not allocated to the DWTC.

公开(公告)号：US20170206173A1

公开(公告)日：2017-07-20

申请号：US14997026

申请日：2016-01-15

Applicant: Futurewei Technologies, Inc.

Inventor： Lee McFearin ,  Sushma Wokhlu ,  Alan Gatherer

IPC: G06F12/12 ,  G06F12/08

CPC classification number: G06F12/121 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/126 ,  G06F2212/1044 ,  G06F2212/60

Abstract: The present disclosure relates to a system and method of managing operation of a cache memory. The system and method assign each nested task a level, and each task within a nested level an instance. Using the assigned task levels and instances, the cache management module is able to determine which cache entries to evict from cache when space is needed, and which evicted cache entries to recover upon completion of preempting tasks.

公开(公告)号：US10884756B2

公开(公告)日：2021-01-05

申请号：US16876995

申请日：2020-05-18

Applicant: Futurewei Technologies, Inc.

Inventor： Sushma Wokhlu ,  Alan Gatherer ,  Ashish Rai Shrivastava

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48

Abstract: A system and method for variable lane architecture includes memory blocks located in a memory bank, one or more computing nodes forming a vector instruction pipeline for executing a task, each of the computing nodes located in the memory bank, each of the computing nodes executing a portion of the task independently of other ones of the computing nodes, and a global program controller unit (GPCU) forming a scalar instruction pipeline for executing the task, the GPCU configured to schedule instructions for the task at one or more of the computing nodes, the GPCU further configured to dispatch an address for the memory blocks used by each of the computing nodes to the computing nodes.

公开(公告)号：US20200278869A1

公开(公告)日：2020-09-03

申请号：US16876995

申请日：2020-05-18

Applicant: Futurewei Technologies, Inc.

Inventor： Sushma Wokhlu ,  Alan Gatherer ,  Ashish Rai Shrivastava

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/48

Abstract: A system and method for variable lane architecture includes memory blocks located in a memory bank, one or more computing nodes forming a vector instruction pipeline for executing a task, each of the computing nodes located in the memory bank, each of the computing nodes executing a portion of the task independently of other ones of the computing nodes, and a global program controller unit (GPCU) forming a scalar instruction pipeline for executing the task, the GPCU configured to schedule instructions for the task at one or more of the computing nodes, the GPCU further configured to dispatch an address for the memory blocks used by each of the computing nodes to the computing nodes.

公开(公告)号：US10452287B2

公开(公告)日：2019-10-22

申请号：US15192453

申请日：2016-06-24

Applicant: Futurewei Technologies, Inc.

Inventor： Sushma Wokhlu ,  Lee Dobson Mcfearin ,  Alan Gatherer ,  Hao Luan

IPC: G06F3/06 ,  G06F12/084 ,  G06F12/0888 ,  G06F12/14 ,  G06F9/50 ,  G06F12/0815

Abstract: It is possible to reduce the latency attributable to memory protection in shared memory systems by performing access protection at a central Data Ownership Manager (DOM), rather than at distributed memory management units in the central processing unit (CPU) elements (CEs) responsible for parallel thread processing. In particular, the DOM may monitor read requests communicated over a data plane between the CEs and a memory controller, and perform access protection verification in parallel with the memory controller's generation of the data response. The DOM may be separate and distinct from both the CEs and the memory controller, and therefore may generally be able to make the access determination without interfering with data plane processing/generation of the read requests and data responses exchanged between the memory controller and the CEs.

公开(公告)号：US20180321939A1

公开(公告)日：2018-11-08

申请号：US15586937

申请日：2017-05-04

Applicant: Futurewei Technologies, Inc.

Inventor： Alan Gatherer ,  Sushma Wokhlu ,  Peter Yan ,  Ywhpyng Harn ,  Ashish Rai Shrivastava ,  Tong Sun ,  Lee Dobson McFearin

IPC: G06F9/30 ,  G06F3/06 ,  G06F9/38

CPC classification number: G06F9/3016 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0673 ,  G06F9/3802

Abstract: Technology for providing data to a processing unit is disclosed. A computer processor may be divided into a master processing unit and consumer processing units. The master processing unit at least partially decodes a machine instruction and determines whether data is needed to execute the machine instruction. The master processing unit sends a request to memory for the data. The request may indicate that the data is to be sent from the memory to a consumer processing unit. The data sent by the memory in response to the request may be stored in local read storage that is close to the consumer processing unit for fast access. The master processing unit may also provide the machine instruction to the consumer processing unit. The consumer processing unit may access the data from the local read storage and execute the machine instruction based on the accessed data.

公开(公告)号：US20170371570A1

公开(公告)日：2017-12-28

申请号：US15192453

申请日：2016-06-24

Applicant: Futurewei Technologies, Inc.

Inventor： Sushma Wokhlu ,  Lee Dobson Mcfearin ,  Alan Gatherer ,  Hao Luan

IPC: G06F3/06 ,  G06F12/084 ,  G06F12/0815

CPC classification number: G06F3/0619 ,  G06F3/0637 ,  G06F3/0673 ,  G06F9/50 ,  G06F9/5016 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0888 ,  G06F12/1466 ,  G06F2212/621

Abstract: It is possible to reduce the latency attributable to memory protection in shared memory systems by performing access protection at a central Data Ownership Manager (DOM), rather than at distributed memory management units in the central processing unit (CPU) elements (CEs) responsible for parallel thread processing. In particular, the DOM may monitor read requests communicated over a data plane between the CEs and a memory controller, and perform access protection verification in parallel with the memory controller's generation of the data response. The DOM may be separate and distinct from both the CEs and the memory controller, and therefore may generally be able to make the access determination without interfering with data plane processing/generation of the read requests and data responses exchanged between the memory controller and the CEs.

公开(公告)号：US20170031689A1

公开(公告)日：2017-02-02

申请号：US15220067

申请日：2016-07-26

Applicant: Futurewei Technologies, Inc.

Inventor： Sushma Wokhlu ,  Alan Gatherer ,  Ashish Rai Shrivastava

IPC: G06F9/38 ,  G06F9/48 ,  G06F9/30

Abstract: A system and method for variable lane architecture includes memory blocks located in a memory bank, one or more computing nodes forming a vector instruction pipeline for executing a task, each of the computing nodes located in the memory bank, each of the computing nodes executing a portion of the task independently of other ones of the computing nodes, and a global program controller unit (GPCU) forming a scalar instruction pipeline for executing the task, the GPCU configured to schedule instructions for the task at one or more of the computing nodes, the GPCU further configured to dispatch an address for the memory blocks used by each of the computing nodes to the computing nodes.

Abstract translation: 用于可变通道架构的系统和方法包括位于存储体中的存储器块，一个或多个计算节点形成用于执行任务的矢量指令流水线，每个计算节点位于存储体中，每个计算节点执行一个 所述任务的一部分独立于所述计算节点中的其他节点，以及形成用于执行所述任务的标量指令流水线的全局程序控制器单元（GPCU），所述GPCU被配置为在所述计算节点的一个或多个处调度所述任务的指令， GPCU还配置为向计算节点分配由每个计算节点使用的存储块的地址。