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    System and Method for Shared Memory Ownership Using Context
    1.
    发明申请
    System and Method for Shared Memory Ownership Using Context 审中-公开

    公开(公告)号：US20200050376A1

    公开(公告)日：2020-02-13

    申请号：US16658899

    申请日：2019-10-21

    Applicant: Futurewei Technologies, Inc.

    Inventor： Sushma Wokhlu ,  Lee Dobson McFearin ,  Alan Gatherer ,  Hao Luan

    IPC: G06F3/06 ,  G06F12/084 ,  G06F12/0888 ,  G06F12/14 ,  G06F9/50

    Abstract: It is possible to reduce the latency attributable to memory protection in shared memory systems by performing access protection at a central Data Ownership Manager (DOM), rather than at distributed memory management units in the central processing unit (CPU) elements (CEs) responsible for parallel thread processing. In particular, the DOM may monitor read requests communicated over a data plane between the CEs and a memory controller, and perform access protection verification in parallel with the memory controller's generation of the data response. The DOM may be separate and distinct from both the CEs and the memory controller, and therefore may generally be able to make the access determination without interfering with data plane processing/generation of the read requests and data responses exchanged between the memory controller and the CEs.

    Shared Memory Controller And Method Of Using Same
    5.
    发明申请
    Shared Memory Controller And Method Of Using Same 审中-公开
    共享内存控制器和使用方法

    公开(公告)号：US20170017412A1

    公开(公告)日：2017-01-19

    申请号：US14797620

    申请日：2015-07-13

    Applicant: Futurewei Technologies, Inc.

    Inventor： Hao Luan ,  Alan Gatherer ,  Bin Yang

    IPC: G06F3/06

    CPC classification number: G06F9/52 ,  G06F3/0613 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0815 ,  G06F13/1663

    Abstract: A controller for a shared memory is disclosed. The controller comprises a transaction scanner configured to scan-in a plurality of transactions to access the shared memory and to divide the transactions into beat-level memory access commands. The controller also comprises a command super-arbiter comprising a plurality of command arbiters corresponding to a plurality of shared memory blocks in the shared memory. The command super-arbiter is configured to access a quality of service for each of the transactions, arbitrate the beat-level memory access commands associated with the transactions based on the quality of service for each of the plurality of transactions, and dispatch the beat-level memory access commands to the shared memory blocks based on results of arbitrating the beat-level memory access commands.

    Abstract translation: 公开了一种用于共享存储器的控制器。 控制器包括交易扫描器，其被配置为扫描多个事务以访问共享存储器并且将事务划分为节​​拍级存储器访问命令。 该控制器还包括一个命令超级仲裁器，其包括与共享存储器中的多个共享存储器块相对应的多个命令仲裁器。 命令超级仲裁器被配置为访问每个事务的服务质量，基于用于多个事务中的每一个的服务质量来仲裁与事务相关联的节拍级存储器访问命令， 基于对节拍级别存储器访问命令进行仲裁的结果，对共享存储器块的级别存储器访问命令。

    System and Method for Shared Memory Ownership Using Context
    6.
    发明申请
    System and Method for Shared Memory Ownership Using Context 有权

    公开(公告)号：US20220164115A1

    公开(公告)日：2022-05-26

    申请号：US17543024

    申请日：2021-12-06

    Applicant: Futurewei Technologies, Inc.

    Inventor： Sushma Wokhlu ,  Lee Dobson McFearin ,  Alan Gatherer ,  Hao Luan

    IPC: G06F3/06 ,  G06F9/50 ,  G06F12/14 ,  G06F12/0888 ,  G06F12/084

    Abstract: It is possible to reduce the latency attributable to memory protection in shared memory systems by performing access protection at a central Data Ownership Manager (DOM), rather than at distributed memory management units in the central processing unit (CPU) elements (CEs) responsible for parallel thread processing. In particular, the DOM may monitor read requests communicated over a data plane between the CEs and a memory controller, and perform access protection verification in parallel with the memory controller's generation of the data response. The DOM may be separate and distinct from both the CEs and the memory controller, and therefore may generally be able to make the access determination without interfering with data plane processing/generation of the read requests and data responses exchanged between the memory controller and the CEs.

    System and method for shared memory ownership using context
    7.
    发明授权
    System and method for shared memory ownership using context 有权

    公开(公告)号：US11194478B2

    公开(公告)日：2021-12-07

    申请号：US16658899

    申请日：2019-10-21

    Applicant: Futurewei Technologies, Inc.

    Inventor： Sushma Wokhlu ,  Lee Dobson McFearin ,  Alan Gatherer ,  Hao Luan

    IPC: G06F3/06 ,  G06F9/50 ,  G06F12/14 ,  G06F12/0888 ,  G06F12/084 ,  G06F12/0815

    Abstract: It is possible to reduce the latency attributable to memory protection in shared memory systems by performing access protection at a central Data Ownership Manager (DOM), rather than at distributed memory management units in the central processing unit (CPU) elements (CEs) responsible for parallel thread processing. In particular, the DOM may monitor read requests communicated over a data plane between the CEs and a memory controller, and perform access protection verification in parallel with the memory controller's generation of the data response. The DOM may be separate and distinct from both the CEs and the memory controller, and therefore may generally be able to make the access determination without interfering with data plane processing/generation of the read requests and data responses exchanged between the memory controller and the CEs.

    DISTRIBUTED AND SHARED MEMORY CONTROLLER
    8.
    发明申请
    DISTRIBUTED AND SHARED MEMORY CONTROLLER 审中-公开

    公开(公告)号：US20180285290A1

    公开(公告)日：2018-10-04

    申请号：US15942065

    申请日：2018-03-30

    Applicant: Futurewei Technologies, Inc.

    Inventor： Hao Luan ,  Alan Gatherer ,  Xi Chen ,  Fang Yu ,  Yichuan Yu ,  Bin Yang ,  Wei Chen

    IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

    Abstract: A distributed and shared memory controller (DSMC) comprises at least one building block. comprising a plurality of switches distributed into a plurality of stages; a plurality of master ports coupled to a first stage of the switches; and a plurality of bank controllers with associated memory banks coupled to a last stage of the switches; wherein each of the switches connects to lower stage switches via internal connections, each of the switches of the first stage connects to at least one of the master ports via master connections and each of the switches of the last stage connects to at least one of the bank controllers via memory connections; wherein each of the switches of the first stage connects to second stage switches of a neighboring building block via outward connections and each of the switches of a second stage connects to first stage switches of the neighboring building block via inward connections.

    INTELLIGENT MEMORY ARCHITECTURE FOR INCREASED EFFICIENCY
    9.
    发明申请
    INTELLIGENT MEMORY ARCHITECTURE FOR INCREASED EFFICIENCY 审中-公开
    提高效率的智能记忆体系结构

    公开(公告)号：US20170031619A1

    公开(公告)日：2017-02-02

    申请号：US14810895

    申请日：2015-07-28

    Applicant: Futurewei Technologies, Inc.

    Inventor： Hao Luan ,  Alan Gatherer ,  Sriram Vishwanath ,  Casen Hunger ,  Hardik Jain

    IPC: G06F3/06

    CPC classification number: G06F3/0622 ,  G06F3/0611 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0688

    Abstract: A method includes receiving a first request, from a first master core, to access data in one of a plurality of memory banks. It is determined whether an access to the data is stalled by virtue of a second request, from a second master core, to access the data in the one of the plurality of memory banks, the second request currently being serviced. In response to a determination that the access to the requested data is stalled, the first request is serviced by accessing data in one of a plurality of coding banks, each coding bank smaller in size than each memory bank.

    Abstract translation: 一种方法包括从第一主核心接收第一请求以访问多个存储器组之一中的数据。 确定通过第二请求从第二主核心访问对数据的访问是否访问多个存储体中的一个存储器中的数据，当前正在服务的第二请求。 响应于对所请求数据的访问被停止的确定，通过访问多个编码组之一中的数据来服务第一请求，每个编码组的尺寸小于每个存储体。

    ACCESS BASED RESOURCES DRIVEN LOW POWER CONTROL AND MANAGEMENT FOR MULTI-CORE SYSTEM ON A CHIP
    10.
    发明申请
    ACCESS BASED RESOURCES DRIVEN LOW POWER CONTROL AND MANAGEMENT FOR MULTI-CORE SYSTEM ON A CHIP 有权
    基于访问的资源驱动芯片上多核系统的低功耗控制和管理

    公开(公告)号：US20160116971A1

    公开(公告)日：2016-04-28

    申请号：US14601981

    申请日：2015-01-21

    Applicant: Futurewei Technologies, Inc.

    Inventor： Hao Luan ,  Alan Gatherer

    IPC: G06F1/32 ,  G06F9/455 ,  G06F9/50

    CPC classification number: G06F1/3287 ,  G06F1/3243 ,  G06F1/329 ,  G06F9/45558 ,  G06F9/5016 ,  G06F9/5094 ,  G06F2009/45583 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/24 ,  Y02D50/20

    Abstract: Function resources/memory resources and an associated resource controller configured to assign a first portion of the function resources/memory resources to at least one processing element in response to an access request from the processing element. The resource controller changes a power mode of the first portion of the function resources/memory resources as a function of the first portion assignment, and leaves an unassigned portion of the function resources/memory resources in a power down mode in a self-governing nature. The resource controller enables the processing element to access the first portion of the function resources/memory resources in response to the access request received from the processing element. The function resources/memory resources, resource controllers and one or more processing elements may comprise a system on a chip (SoC).

    Abstract translation: 功能资源/存储器资源和相关联的资源控制器被配置为响应于来自处理元件的访问请求，将功能资源/存储器资源的第一部分分配给至少一个处理元件。 资源控制器根据第一部分分配改变功能资源/存储器资源的第一部分的功率模式，并且将功能资源/存储器资源的未分配部分置于自主控制模式中 。 资源控制器使得处理元件能够响应于从处理元件接收的访问请求来访问功能资源/存储器资源的第一部分。 功能资源/存储器资源，资源控制器和一个或多个处理元件可以包括芯片上的系统（SoC）。

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