公开(公告)号：US20140273306A1

公开(公告)日：2014-09-18

申请号：US13832994

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Sudharshanan Raghunathan

IPC: H01L21/66

CPC classification number: H01L22/10 ,  G03F1/70 ,  G03F1/72 ,  G03F1/76

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes patterning a first photoresist layer overlying a mask blank that is mounted on a first chuck to form a first patterned photoresist layer. The mask blank is selectively etched using the first patterned photoresist layer to form a first patterned mask. The first patterned mask is mounted on a second chuck and a non-flatness compensation is determined. The first patterned mask is mounted on the first chuck and a second photoresist layer is patterned overlying the first patterned mask to form a second patterned photoresist layer. The second patterned photoresist layer includes a device pattern that has been adjusted using the non-flatness compensation. The first patterned mask is selectively etched using the second patterned photoresist layer to form a second patterned mask.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括图案化覆盖在掩模板上的第一光致抗蚀剂层，该第一光致抗蚀剂层安装在第一卡盘上以形成第一图案化光致抗蚀剂层。 使用第一图案化的光致抗蚀剂层选择性地蚀刻掩模空白以形成第一图案化掩模。 第一图案掩模安装在第二卡盘上，并且确定非平坦度补偿。 第一图案化掩模安装在第一卡盘上，并且将第二光致抗蚀剂层图案化成覆盖在第一图案化掩模上以形成第二图案化光刻胶层。 第二图案化光致抗蚀剂层包括已经使用非平坦度补偿来调节的装置图案。 使用第二图案化的光致抗蚀剂层选择性地蚀刻第一图案化掩模以形成第二图案化掩模。

公开(公告)号：US20140272677A1

公开(公告)日：2014-09-18

申请号：US13840790

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Sudharshanan Raghunathan ,  Pawitter Mangat ,  Hui Peng Koh

IPC: G03F7/20 ,  G03F1/22

CPC classification number: G03F7/2022 ,  G03F1/22

Abstract: A method for fabricating integrated circuits includes fabricating an EUV mask by providing a photomask having a border region. A photoresist is formed over the photomask and has a border region overlying the border region of the photomask. The method exposes an inner portion and an outer portion of the photoresist border region. The method removes the inner portion and the outer portion to expose the border region of the photomask. The border region of the photomask is etched using the photoresist as a mask to form the EUV mask with a non-reflective border. The photoresist is removed from the EUV mask. The method includes forming another photoresist over a partially-fabricated integrated circuit layer and patterning the photoresist by exposure to EUV light reflected from the EUV mask to expose portions of the partially-fabricated integrated circuit layer. Portions of the partially-fabricated integrated circuit layer and the photoresist are removed.

Abstract translation: 制造集成电路的方法包括通过提供具有边界区域的光掩模来制造EUV掩模。 在光掩模上形成光致抗蚀剂，并且具有覆盖在光掩模的边界区域上的边界区域。 该方法曝光光刻胶边界区域的内部部分和外部部分。 该方法移除内部部分和外部部分以暴露光掩模的边界区域。 使用光致抗蚀剂作为掩模蚀刻光掩模的边界区域，以形成具有非反射边界的EUV掩模。 从EUV掩模中去除光致抗蚀剂。 该方法包括在部分制造的集成电路层上形成另一光致抗蚀剂，并通过暴露于从EUV掩模反射的EUV光来图案化光致抗蚀剂，以暴露部分制造的集成电路层的部分。 去除部分制造的集成电路层和光致抗蚀剂的部分。

公开(公告)号：US20170263506A1

公开(公告)日：2017-09-14

申请号：US15067953

申请日：2016-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Tuhin Guha Neogi ,  Andy Chi-Hung Wei ,  Jia Zeng ,  Jongwook Kye ,  Jason Eugene Stephens ,  Irene Yuh-Ling Lin ,  Sudharshanan Raghunathan ,  Lei Yuan

IPC: H01L21/8238 ,  H01L21/768 ,  G06F17/50 ,  H01L21/027 ,  H01L27/092 ,  H01L23/535 ,  H01L21/8234 ,  H01L21/285

CPC classification number: H01L21/823871 ,  G06F17/5072 ,  H01L21/027 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/0924

Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.

公开(公告)号：US09478506B2

公开(公告)日：2016-10-25

申请号：US13787090

申请日：2013-03-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Richard A. Farrell ,  Gerard M. Schmid ,  Sudharshanan Raghunathan

IPC: H01L21/311 ,  H01L23/00 ,  H01L21/308 ,  H01L21/683 ,  H01L21/768 ,  H01L21/67

CPC classification number: H01L23/564 ,  H01L21/3086 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/67109 ,  H01L21/6831 ,  H01L21/76807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Approaches for multilayer pattern transfer for chemical guides are provided. In a typical embodiment, a device is formed by forming an etch mask layer (e.g., a nitride layer and an oxide layer) over a substrate (e.g., silicon (Si)). An orientation control layer (e.g., a neutral layer) is then formed over the etch mask layer, and an ARC layer (e.g., SiARC) is formed over the orientation control layer. In other embodiments, an organic planarization layer (OPL) and/or a protection layer may also be formed between the ARC layer and the orientation control layer. Regardless, a tapered etch profile/pattern may then be formed through the ARC and/or other layers.

Abstract translation: 提供了用于化学导轨的多层图案转印的方法。 在典型的实施例中，通过在衬底（例如，硅（Si））上形成蚀刻掩模层（例如，氮化物层和氧化物层）来形成器件。 然后在蚀刻掩模层上形成取向控制层（例如中性层），并且在取向控制层上形成ARC层（例如SiARC）。 在其它实施例中，也可以在ARC层和取向控制层之间形成有机平坦化层（OPL）和/或保护层。 无论如何，可以通过ARC和/或其他层形成锥形蚀刻轮廓/图案。

公开(公告)号：US08956789B2

公开(公告)日：2015-02-17

申请号：US13832994

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Sudharshanan Raghunathan

IPC: H01L21/66

CPC classification number: H01L22/10 ,  G03F1/70 ,  G03F1/72 ,  G03F1/76

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes patterning a first photoresist layer overlying a mask blank that is mounted on a first chuck to form a first patterned photoresist layer. The mask blank is selectively etched using the first patterned photoresist layer to form a first patterned mask. The first patterned mask is mounted on a second chuck and a non-flatness compensation is determined. The first patterned mask is mounted on the first chuck and a second photoresist layer is patterned overlying the first patterned mask to form a second patterned photoresist layer. The second patterned photoresist layer includes a device pattern that has been adjusted using the non-flatness compensation. The first patterned mask is selectively etched using the second patterned photoresist layer to form a second patterned mask.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括图案化覆盖在掩模板上的第一光致抗蚀剂层，该第一光致抗蚀剂层安装在第一卡盘上以形成第一图案化光致抗蚀剂层。 使用第一图案化的光致抗蚀剂层选择性地蚀刻掩模空白以形成第一图案化掩模。 第一图案掩模安装在第二卡盘上，并且确定非平坦度补偿。 第一图案化掩模安装在第一卡盘上，并且将第二光致抗蚀剂层图案叠加在第一图案化掩模上，以形成第二图案化光刻胶层。 第二图案化光致抗蚀剂层包括已经使用非平坦度补偿来调节的装置图案。 使用第二图案化的光致抗蚀剂层选择性地蚀刻第一图案化掩模以形成第二图案化掩模。

公开(公告)号：US20140252660A1

公开(公告)日：2014-09-11

申请号：US13787090

申请日：2013-03-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Richard A. Farrell ,  Gerard M. Schmid ,  Sudharshanan Raghunathan

IPC: H01L21/311 ,  H01L23/00

CPC classification number: H01L23/564 ,  H01L21/3086 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/67109 ,  H01L21/6831 ,  H01L21/76807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Approaches for multilayer pattern transfer for chemical guides are provided. In a typical embodiment, a device is formed by forming an etch mask layer (e.g., a nitride layer and an oxide layer) over a substrate (e.g., silicon (Si)). An orientation control layer (e.g., a neutral layer) is then formed over the etch mask layer, and an ARC layer (e.g., SiARC) is formed over the orientation control layer. In other embodiments, an organic planarization layer (OPL) and/or a protection layer may also be formed between the ARC layer and the orientation control layer. Regardless, a tapered etch profile/pattern may then be formed through the ARC and/or other layers.

Abstract translation: 提供了用于化学导轨的多层图案转印的方法。 在典型的实施例中，通过在衬底（例如，硅（Si））上形成蚀刻掩模层（例如，氮化物层和氧化物层）来形成器件。 然后在蚀刻掩模层上形成取向控制层（例如中性层），并且在取向控制层上形成ARC层（例如SiARC）。 在其它实施例中，也可以在ARC层和取向控制层之间形成有机平坦化层（OPL）和/或保护层。 无论如何，可以通过ARC和/或其他层形成锥形蚀刻轮廓/图案。