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公开(公告)号:US10784119B2
公开(公告)日:2020-09-22
申请号:US16154306
申请日:2018-10-08
Applicant: GLOBALFOUNDRIES Inc.
Inventor: Ravi Prakash Srivastava , Hsueh-Chung Chen , Steven McDermott , Martin O'Toole , Brendan O'Brien , Terry A. Spooner
IPC: H01L21/308 , H01L21/311 , H01L21/033 , H01L21/768
Abstract: Methods of self-aligned multiple patterning. First and second mandrels are formed over a hardmask, and a conformal spacer layer is deposited over the first mandrel, the second mandrel, and the hardmask between the first mandrel and the second mandrel. A planarizing layer is patterned to form first and second trenches that expose first and second lengthwise portions of the conformal spacer layer respectively between the first and second mandrels. After patterning the planarizing layer, the first and second lengthwise portions of the conformal spacer layer are removed with an etching process to expose respective portions of the hardmask along a non-mandrel line. A third lengthwise portion of the conformal spacer layer is masked during the etching process by a portion of the planarizing layer and defines a non-mandrel etch mask.
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公开(公告)号:US10566231B2
公开(公告)日:2020-02-18
申请号:US15966032
申请日:2018-04-30
Applicant: GLOBALFOUNDRIES INC.
Inventor: Martin J. O'Toole , Christopher J. Penny , Jae O. Choo , Adam L. da Silva , Craig Child , Terry A. Spooner , Hsueh-Chung Chen , Brendan O'Brien , Keith P. Donegan
IPC: H01L21/768 , H01L23/532
Abstract: Methods of forming an interconnect of an IC are disclosed. The methods include forming a first interlayer dielectric (ILD) layer and a second ILD layer with an ILD etch stop layer (ESL) therebetween. The ILD ESL has an etch rate that is at least five times slower than the first and second ILD layers, and may include, for example, aluminum oxynitride. A dual damascene (DD) hard mask is used to form a wire trench opening in the second ILD layer and a via opening in the first ILD layer, creating a via-wire opening. Due to the slower etch rate, the ILD ESL defines the via opening in the first ILD layer as a chamferless via opening. A unitary via-wire conductive structure coupled to the conductive structure in the via-wire opening can be formed from the via-wire opening.
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公开(公告)号:US20190333805A1
公开(公告)日:2019-10-31
申请号:US15966032
申请日:2018-04-30
Applicant: GLOBALFOUNDRIES INC.
Inventor: Martin J. O'Toole , Christopher J. Penny , Jae O. Choo , Adam L. da Silva , Craig Child , Terry A. Spooner , Hsueh-Chung Chen , Brendan O'Brien , Keith P. Donegan
IPC: H01L21/768
Abstract: Methods of forming an interconnect of an IC are disclosed. The methods include forming a first interlayer dielectric (ILD) layer and a second ILD layer with an ILD etch stop layer (ESL) therebetween. The ILD ESL has an etch rate that is at least five times slower than the first and second ILD layers, and may include, for example, aluminum oxynitride. A dual damascene (DD) hard mask is used to form a wire trench opening in the second ILD layer and a via opening in the first ILD layer, creating a via-wire opening. Due to the slower etch rate, the ILD ESL defines the via opening in the first ILD layer as a chamferless via opening. A unitary via-wire conductive structure coupled to the conductive structure in the via-wire opening can be formed from the via-wire opening.
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公开(公告)号:US10340180B1
公开(公告)日:2019-07-02
申请号:US15872314
申请日:2018-01-16
Applicant: GLOBALFOUNDRIES INC.
Inventor: Hsueh-Chung Chen , Martin J. O'Toole , Terry A. Spooner , Jason E. Stephens
IPC: H01L21/768 , H01L23/522 , H01L23/528 , H01L21/033 , H01L23/532
CPC classification number: H01L21/76816 , H01L21/0335 , H01L21/0337 , H01L21/76877 , H01L23/5226 , H01L23/5286 , H01L23/53209 , H01L23/53228 , H01L23/53242 , H01L23/53257 , H01L23/53271
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to merged mandrel lines and methods of manufacture. The structure includes: at least one metal line having a first dimension in a self-aligned double patterning (SADP) line array; and at least one metal line having a second dimension inserted into the SADP line array, the second dimension being different than the first dimension.
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公开(公告)号:US20190139823A1
公开(公告)日:2019-05-09
申请号:US15804006
申请日:2017-11-06
Applicant: GLOBALFOUNDRIES Inc.
Inventor: Hsueh-Chung Chen , Jason E. Stephens , Lars W. Liebmann , Guillaume Bouche
IPC: H01L21/768 , H01L23/528 , H01L23/522 , H01L21/3213
Abstract: One illustrative method disclosed herein may include forming first and second via openings and forming conductive material for first and second conductive vias across substantially an entirety of an upper surface of a layer of insulating material and in the via openings. A patterned line etch mask layer is then formed above the conductive material, the etch mask having a first feature corresponding to a first conductive line and a second feature corresponding to a second conductive line, and performing at least one etching process to define the first and second conductive lines that are arranged in a tip-to-tip configuration. In this example, a first edge of the first conductive via is substantially aligned with a first end of the first conductive line and a second edge of the second conductive via is substantially aligned with a second end of the second conductive line.
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公开(公告)号:US09257334B2
公开(公告)日:2016-02-09
申请号:US14837865
申请日:2015-08-27
Inventor: Hsueh-Chung Chen , Yongan Xu , Yunpeng Yin , Ailian Zhao
IPC: H01L21/4763 , H01L21/768 , H01L21/033 , H01L21/311
CPC classification number: H01L21/76802 , H01L21/0332 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76811 , H01L21/76816 , H01L21/76897 , H01L21/76898
Abstract: A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer.
Abstract translation: 一种包括在衬底上形成五层硬掩模的方法,所述五层硬掩模包括在第二硬掩模层上方的第一硬掩模层; 在第一硬掩模层中形成沟槽图案; 将第一通孔条图案从五层硬掩模上方的第一光致抗蚀剂层转移到第二硬掩模层中,产生第一通孔图案,第二硬掩模层中的第一通孔图案与沟槽图案重叠并且在 双面通过第一个硬掩模层中的沟槽图案; 以及将所述第一通孔图案从所述第二硬掩模层转移到所述衬底中,从而产生自对准的通孔,所述自对准通孔开口通过所述第二硬掩模层中的所述第一通孔图案在所有侧面上自对准。
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公开(公告)号:US10651046B2
公开(公告)日:2020-05-12
申请号:US16154237
申请日:2018-10-08
Applicant: GLOBALFOUNDRIES Inc.
Inventor: Hsueh-Chung Chen , Brendan O'Brien , Martin O'Toole , Keith Donegan
IPC: H01L21/311 , H01L21/768 , H01L21/033
Abstract: Methods of self-aligned multiple patterning. A mandrel is formed over a hardmask, and a planarizing layer is formed over the mandrel and the hardmask. The planarizing layer is patterned to form first and second trenches exposing respective first and second lengthwise sections of the mandrel. A portion of the patterned planarizing layer covers a third lengthwise section of the mandrel arranged between the first and second lengthwise sections of the mandrel. After patterning the planarizing layer, the first and second lengthwise sections of the mandrel are removed with an etching process to define a pattern including a mandrel line exposing respective first portions of the hardmask. The third lengthwise section of the mandrel is masked by the portion of the planarizing layer during the etching process, and the third lengthwise section covers a second portion of the hardmask arranged along the mandrel line between the first portions of the hardmask.
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公开(公告)号:US09653571B2
公开(公告)日:2017-05-16
申请号:US14739662
申请日:2015-06-15
Applicant: International Business Machines Corporation , Samsung Electronics Co., Ltd. , GLOBALFOUNDRIES Inc.
Inventor: Hsueh-Chung Chen , Su Chen Fan , Dong Kwon Kim , Sean Lian , Fee Li Lie , Linus Jang
IPC: H01L29/06 , H01L29/66 , H01L21/311 , H01L21/02 , H01L21/308
CPC classification number: H01L29/6653 , H01L21/02178 , H01L21/02181 , H01L21/02183 , H01L21/02186 , H01L21/3086 , H01L21/31116
Abstract: An aspect of the invention includes a freestanding spacer having a sub-lithographic dimension for a sidewall image transfer process. The freestanding spacer comprises: a first spacer layer having a first portion disposed on the semiconductor layer; and a second spacer layer having a first surface disposed on the first portion of the first spacer layer, wherein the first spacer layer has a first dielectric constant and the second spacer layer has a second dielectric constant, the first dielectric constant being greater than the second dielectric constant, and wherein a dimension of each of the first and second spacer layers collectively determine the sub-lithographic lateral dimension of the freestanding spacer.
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公开(公告)号:US20150371896A1
公开(公告)日:2015-12-24
申请号:US14837827
申请日:2015-08-27
Inventor: Hsueh-Chung Chen , Yongan Xu , Yunpeng Yin , Ailian Zhao
IPC: H01L21/768
CPC classification number: H01L21/76802 , H01L21/0332 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76811 , H01L21/76816 , H01L21/76897 , H01L21/76898
Abstract: A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer.
Abstract translation: 一种包括在衬底上形成五层硬掩模的方法,所述五层硬掩模包括在第二硬掩模层上方的第一硬掩模层; 在第一硬掩模层中形成沟槽图案; 将第一通孔条图案从五层硬掩模上方的第一光致抗蚀剂层转移到第二硬掩模层中,产生第一通孔图案,第二硬掩模层中的第一通孔图案与沟槽图案重叠并且在 双面通过第一个硬掩模层中的沟槽图案; 以及将所述第一通孔图案从所述第二硬掩模层转移到所述衬底中,从而产生自对准的通孔,所述自对准通孔开口通过所述第二硬掩模层中的所述第一通孔图案在所有侧面上自对准。
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