公开(公告)号：US09548381B1

公开(公告)日：2017-01-17

申请号：US14967946

申请日：2015-12-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan ,  Jeffrey W. Sleight

IPC: H01L29/45 ,  H01L29/267 ,  H01L29/66 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/66977 ,  H01L29/0673 ,  H01L29/267 ,  H01L29/66356 ,  H01L29/66742 ,  H01L29/7391 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78681 ,  H01L29/78696

Abstract: A heterojunction tunnel field effect transistor (TFET) has a channel region that includes a first portion of a nanowire, a source region and a drain region that respectively include a second portion and a third portion of a nanowire, and a gate that surrounds the channel region, where the first portion of the nanowire comprises an intrinsic, epitaxial III-V semiconductor. The TFET can be made by selectively etching the epitaxial underlayer to define a tethered (suspended) nanowire that forms a channel region of the device. Source and drain regions can be formed from regrown p-type and n-type epitaxial layers.

Abstract translation: 异质结隧道场效应晶体管（TFET）具有沟道区，该沟道区包括分别包括纳米线的第二部分和第三部分的纳米线的第一部分，源极区和漏极区，以及包围沟道的栅极 区域，其中纳米线的第一部分包括本征的外延III-V半导体。 可以通过选择性地蚀刻外延底层来形成TFET，以限定形成该器件的沟道区的系留（悬挂）的纳米线。 源极和漏极区可以由再生长的p型和n型外延层形成。

公开(公告)号：US09443951B2

公开(公告)日：2016-09-13

申请号：US14076387

申请日：2013-11-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey W. Sleight

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/66484 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7848 ,  H01L29/785

Abstract: Fin-defining mask structures are formed over a semiconductor material layer having a first semiconductor material and a disposable gate structure is formed thereupon. A gate spacer is formed around the disposable gate structure and physically exposed portions of the fin-defining mask structures are subsequently removed. The semiconductor material layer is recessed employing the disposable gate structure and the gate spacer as an etch mask to form recessed semiconductor material portions. Embedded planar source/drain stressors are formed on the recessed semiconductor material portions by selective deposition of a second semiconductor material having a different lattice constant than the first semiconductor material. After formation of a planarization dielectric layer, the disposable gate structure is removed. A plurality of semiconductor fins are formed employing the fin-defining mask structures as an etch mask. A replacement gate structure is formed on the plurality of semiconductor fins.

公开(公告)号：US09224866B2

公开(公告)日：2015-12-29

申请号：US14010589

申请日：2013-08-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anirban Basu ,  Guy Cohen ,  Amlan Majumdar ,  Jeffrey W. Sleight

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L21/265 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31055 ,  H01L21/76802 ,  H01L21/76879 ,  H01L29/41733 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor fin including a vertical stack, from bottom to top, of a second semiconductor material and a first semiconductor material is formed on a substrate. A disposable gate structure straddling the semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask, At least one semiconductor shell layer or a semiconductor cap layer can be formed as an etch stop structure. A planarization dielectric layer is subsequently formed. A gate cavity is formed by removing the disposable gate structure. A portion of the second semiconductor material is removed selective to the first semiconductor material within the gate cavity so that a middle portion of the semiconductor fin becomes suspended over the substrate. A gate dielectric layer and a gate electrode are sequentially formed. The gate electrode laterally surrounds a body region of a fin field effect transistor.

Abstract translation: 在基板上形成包括第二半导体材料和第一半导体材料的从底部到顶部的垂直叠层的半导体鳍片。 形成跨越半导体鳍片的一次性栅极结构。 使用一次性栅极结构作为注入掩模形成源区和漏区，可以形成至少一个半导体外壳层或半导体盖层作为蚀刻停止结构。 随后形成平坦化介电层。 通过去除一次性栅极结构形成栅极腔。 第二半导体材料的一部分被选择性地移除到栅极腔内的第一半导体材料，使得半导体鳍片的中间部分悬浮在衬底上。 依次形成栅介质层和栅电极。 栅电极横向围绕鳍场效应晶体管的体区。