公开(公告)号：US09431494B2

公开(公告)日：2016-08-30

申请号：US14739137

申请日：2015-06-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anirban Basu ,  Guy Cohen ,  Amlan Majumdar

IPC: H01L29/41 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L21/28 ,  H01L21/283 ,  H01L29/10 ,  H01L29/201 ,  H01L29/417

CPC classification number: H01L29/42356 ,  H01L21/28026 ,  H01L21/283 ,  H01L29/1054 ,  H01L29/201 ,  H01L29/41783 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: A disposable gate structure straddling a semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask. A planarization dielectric layer is formed such that a top surface of the planarization dielectric layer is coplanar with the disposable gate structure. A gate cavity is formed by removing the disposable gate structure. An epitaxial cap layer is deposited on physically exposed semiconductor surfaces of the semiconductor fin by selective epitaxy. A gate dielectric layer is formed on the epitaxial cap layer, and a gate electrode can be formed by filling the gate cavity. The epitaxial cap layer can include a material that reduces the density of interfacial defects at an interface with the gate dielectric layer.

公开(公告)号：US09397195B2

公开(公告)日：2016-07-19

申请号：US14064830

申请日：2013-10-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guy Cohen ,  Christos D. Dimitrakopoulos ,  Alfred Grill

IPC: H01L29/775 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/306 ,  H01L21/02 ,  H01L21/324 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L51/00 ,  H01L21/28 ,  H01L29/78 ,  H01L51/05 ,  B82Y99/00

CPC classification number: H01L29/66795 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y99/00 ,  H01L21/02057 ,  H01L21/02381 ,  H01L21/02527 ,  H01L21/02529 ,  H01L21/02636 ,  H01L21/28008 ,  H01L21/30604 ,  H01L21/31051 ,  H01L21/324 ,  H01L29/0673 ,  H01L29/1025 ,  H01L29/1606 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66787 ,  H01L29/775 ,  H01L29/785 ,  H01L51/0045 ,  H01L51/0048 ,  H01L51/0558

Abstract: Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed.

公开(公告)号：US20160099329A1

公开(公告)日：2016-04-07

申请号：US14968061

申请日：2015-12-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anirban Basu ,  Guy Cohen ,  Amlan Majumdar ,  Jeffrey W. Sleight

IPC: H01L29/423 ,  H01L21/31 ,  H01L21/306 ,  H01L21/768 ,  H01L21/265 ,  H01L21/3105 ,  H01L29/417 ,  H01L29/66 ,  H01L21/283

CPC classification number: H01L29/42392 ,  H01L21/265 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31055 ,  H01L21/76802 ,  H01L21/76879 ,  H01L29/41733 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor fin including a vertical stack, from bottom to top, of a second semiconductor material and a first semiconductor material is formed on a substrate. A disposable gate structure straddling the semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask, At least one semiconductor shell layer or a semiconductor cap layer can be formed as an etch stop structure. A planarization dielectric layer is subsequently formed. A gate cavity is formed by removing the disposable gate structure. A portion of the second semiconductor material is removed selective to the first semiconductor material within the gate cavity so that a middle portion of the semiconductor fin becomes suspended over the substrate. A gate dielectric layer and a gate electrode are sequentially formed. The gate electrode laterally surrounds a body region of a fin field effect transistor.

公开(公告)号：US09224866B2

公开(公告)日：2015-12-29

申请号：US14010589

申请日：2013-08-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anirban Basu ,  Guy Cohen ,  Amlan Majumdar ,  Jeffrey W. Sleight

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L21/265 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31055 ,  H01L21/76802 ,  H01L21/76879 ,  H01L29/41733 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor fin including a vertical stack, from bottom to top, of a second semiconductor material and a first semiconductor material is formed on a substrate. A disposable gate structure straddling the semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask, At least one semiconductor shell layer or a semiconductor cap layer can be formed as an etch stop structure. A planarization dielectric layer is subsequently formed. A gate cavity is formed by removing the disposable gate structure. A portion of the second semiconductor material is removed selective to the first semiconductor material within the gate cavity so that a middle portion of the semiconductor fin becomes suspended over the substrate. A gate dielectric layer and a gate electrode are sequentially formed. The gate electrode laterally surrounds a body region of a fin field effect transistor.

Abstract translation: 在基板上形成包括第二半导体材料和第一半导体材料的从底部到顶部的垂直叠层的半导体鳍片。 形成跨越半导体鳍片的一次性栅极结构。 使用一次性栅极结构作为注入掩模形成源区和漏区，可以形成至少一个半导体外壳层或半导体盖层作为蚀刻停止结构。 随后形成平坦化介电层。 通过去除一次性栅极结构形成栅极腔。 第二半导体材料的一部分被选择性地移除到栅极腔内的第一半导体材料，使得半导体鳍片的中间部分悬浮在衬底上。 依次形成栅介质层和栅电极。 栅电极横向围绕鳍场效应晶体管的体区。

公开(公告)号：US09337264B2

公开(公告)日：2016-05-10

申请号：US14664435

申请日：2015-03-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sarunya Bangsaruntip ,  Guy Cohen ,  Michael A. Guillorn

IPC: H01L29/786 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/165 ,  H01L29/78 ,  H01L21/285

CPC classification number: H01L29/0669 ,  B82Y10/00 ,  H01L21/28518 ,  H01L29/0649 ,  H01L29/0665 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/775 ,  H01L29/7831 ,  H01L29/78645 ,  H01L29/78696

Abstract: Techniques for defining a damascene gate in nanowire FET devices are provided. In one aspect, a method of fabricating a FET device is provided including the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are patterned in the SOI layer in a ladder-like configuration. The BOX is recessed under the nanowires. A patternable dielectric dummy gate(s) is formed over the recessed BOX and surrounding a portion of each of the nanowires. A CMP stop layer is deposited over the dummy gate(s) and the source and drain regions. A dielectric film is deposited over the CMP stop layer. The dielectric film is planarized using CMP to expose the dummy gate(s). The dummy gate(s) is at least partially removed so as to release the nanowires in a channel region. The dummy gate(s) is replaced with a gate conductor material.