公开(公告)号：US09472402B2

公开(公告)日：2016-10-18

申请号：US14487213

申请日：2014-09-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Deok-kee Kim ,  Kenneth T. Settlemyer, Jr. ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Dirk Pfeiffer ,  Timothy J. Dalton ,  Katherina E. Babich ,  Arpan P. Mohorowala ,  Harald Okorn-Schmidt

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  G03F7/11

CPC classification number: H01L21/0337 ,  G03F7/11 ,  H01L21/027 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/0338 ,  H01L21/31144

Abstract: Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.

公开(公告)号：US20160190140A1

公开(公告)日：2016-06-30

申请号：US14582655

申请日：2014-12-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Benjamin Ryan Cipriany ,  Ramachandra Divakaruni ,  Brian J. Greene ,  Ali Khakifirooz ,  Byeong Yeol Kim ,  William Larsen Nicoll

IPC: H01L27/108 ,  H01L21/84 ,  H01L21/02 ,  H01L21/285 ,  H01L21/324 ,  H01L21/311

CPC classification number: H01L27/10829 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/76895 ,  H01L21/845 ,  H01L27/10826 ,  H01L27/10867 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/945

Abstract: Structures and methods for deep trench capacitor connections are disclosed. The structure includes a reduced diameter top portion of the capacitor conductor. This increases the effective spacing between neighboring deep trench capacitors. Silicide or additional polysilicon are then deposited to complete the connection between the deep trench capacitor and a neighboring transistor.

Abstract translation: 公开了用于深沟槽电容器连接的结构和方法。 该结构包括电容器导体的直径减小的顶部。 这增加了相邻深沟槽电容器之间的有效间隔。 然后沉积硅化物或附加的多晶硅以完成深沟槽电容器和相邻晶体管之间的连接。

公开(公告)号：US09245981B2

公开(公告)日：2016-01-26

申请号：US14808914

申请日：2015-07-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Bruce B. Doris ,  Ali Khakifirooz ,  Edward J. Nowak ,  Kern Rim

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/785

Abstract: An array of stacks containing a semiconductor fins and an oxygen-impermeable cap is formed on a semiconductor substrate with a substantially uniform areal density. Oxygen-impermeable spacers are formed around each stack, and the semiconductor substrate is etched to vertically extend trenches. Semiconductor sidewalls are physically exposed from underneath the oxygen-impermeable spacers. The oxygen-impermeable spacers are removed in regions in which semiconductor fins are not needed. A dielectric oxide material is deposited to fill the trenches. Oxidation is performed to convert a top portion of the semiconductor substrate and semiconductor fins not protected by oxygen-impermeable spacers into dielectric material portions. Upon removal of the oxygen-impermeable caps and remaining oxygen-impermeable spacers, an array including semiconductor fins and dielectric fins is provided. The dielectric fins alleviate variations in the local density of protruding structures, thereby reducing topographical variations in the height of gate level structures to be subsequently formed.

公开(公告)号：US09209094B2

公开(公告)日：2015-12-08

申请号：US13952993

申请日：2013-07-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L27/00 ,  H01L21/00 ,  H01L21/84 ,  H01L29/78 ,  H01L27/12

CPC classification number: H01L21/845 ,  H01L27/1211 ,  H01L29/7848

Abstract: A first fin field effect transistor and a second fin field effect transistor are formed on an insulator layer overlying a semiconductor material layer. A first pair of trenches is formed through the insulator layer in regions in which a source region and a drain region of the first fin field effect transistor is to be formed. A second pair of trenches is formed partly into the insulator layer without extending to the top surface of the semiconductor material layer. The source region and the drain region of the first field effect transistor can be epitaxial stressor material portions that are anchored to, and epitaxially aligned to, the semiconductor material layer and apply stress to the channel of the first field effect transistor to enhance performance. The insulator layer provides electrical isolation from the semiconductor material layer to the second field effect transistor.

Abstract translation: 第一鳍状场效应晶体管和第二鳍状场效应晶体管形成在覆盖半导体材料层的绝缘体层上。 在要形成第一鳍式场效应晶体管的源极区域和漏极区域的区域中，通过绝缘体层形成第一对沟槽。 第二对沟槽部分地形成绝缘体层，而不延伸到半导体材料层的顶表面。 第一场效应晶体管的源极区域和漏极区域可以是外延应力材料部分，其被锚定并外延对准半导体材料层，并且将应力施加到第一场效应晶体管的沟道以增强性能。 绝缘体层提供从半导体材料层到第二场效应晶体管的电隔离。