公开(公告)号：US20200126863A1

公开(公告)日：2020-04-23

申请号：US16668500

申请日：2019-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Scott Beasor ,  Haiting Wang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

Abstract: One illustrative device disclosed includes a gate structure and a sidewall spacer positioned adjacent the gate structure, the sidewall spacer having an upper surface, wherein an upper portion of the gate structure is positioned above a level of the upper surface of the sidewall spacer. In this illustrative example, the device also includes a tapered upper surface on the upper portion of the gate structure and a gate cap, the gate cap being positioned above the tapered upper surface of the gate structure and above the upper surface of the sidewall spacer.

公开(公告)号：US10586736B2

公开(公告)日：2020-03-10

申请号：US16005073

申请日：2018-06-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Ruilong Xie ,  Shesh Mani Pandey ,  Hui Zang ,  Garo Jacques Derderian ,  Scott Beasor

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L27/02 ,  H01L21/308 ,  H01L21/762

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a hybrid fin cut with improved fin profiles and methods of manufacture. The structure includes: a plurality of fin structures in a first region of a first density of fin structures; a plurality of fin structures in a second region of a second density of fin structures; and a plurality of fin structures in a third region of a third density of fin structures. The first density, second density and third density of fin structures are different densities of fin structures, and the plurality of fin structures in the first region, the second region and the third region have a substantially uniform profile.

公开(公告)号：US10049944B2

公开(公告)日：2018-08-14

申请号：US15285978

申请日：2016-10-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Scott Beasor ,  Jeremy A. Wahl

IPC: H01L29/41 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423

Abstract: A method for integrating nanostructures in finFET processing and a related device are provided. Embodiments include forming fins in a Si substrate in first and second device regions; forming STI regions in spaces between fins; forming a first hardmask over the fins and STI regions; removing a portion of the first hardmask over the first device region to expose upper surfaces of the fins and STI regions in the first device region; recessing an upper portion of the fins; forming first devices over the recessed fins; forming a second hardmask over the fins and STI regions; removing a portion of the second hardmask over the second device region to expose upper surfaces of the fins and STI regions; recessing an upper portion of the fins; and forming second devices, different from the first devices, over the recessed fins, wherein the first and/or second devices include nanowire or nanosheet devices.

公开(公告)号：US10043708B2

公开(公告)日：2018-08-07

申请号：US15347119

申请日：2016-11-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Viraj Sardesai ,  Suraj K. Patil ,  Scott Beasor ,  Vimal Kumar Kamineni

IPC: H01L29/40 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation.

公开(公告)号：US09812453B1

公开(公告)日：2017-11-07

申请号：US15431334

申请日：2017-02-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George R. Mulfinger ,  Lakshmanan H. Vanamurthy ,  Scott Beasor ,  Timothy J. McArdle ,  Judson R. Holt ,  Hao Zhang

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/285 ,  H01L21/02 ,  H01L29/66 ,  H01L29/45 ,  H01L29/167 ,  H01L29/165 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/456 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7848

Abstract: A method for forming a self-aligned sacrificial epitaxial cap for trench silicide and the resulting device are provided. Embodiments include forming a Si fin in a PFET region and a pair of Si fins in a NFET region; forming epitaxial S/D regions; forming a spacer over the S/D region in the PFET region; forming a sacrificial cap over the S/D regions in the NFET region, merging the pair of Si fins; removing the spacer from the S/D region in the PFET region; forming silicide trenches over the S/D regions in the PFET and NEFT regions; implanting dopant into the S/D region in the PFET region while the sacrificial cap protects the S/D regions in the NFET region; removing the sacrificial cap; and forming a metal layer over top surfaces of the S/D region in the PFET region and top and bottom surfaces of the S/D regions in the NFET region.

公开(公告)号：US09397004B2

公开(公告)日：2016-07-19

申请号：US14164582

申请日：2014-01-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Guillaume Bouche ,  Erik Geiss ,  Scott Beasor ,  Andy Wei ,  Deniz Elizabeth Civay

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/027 ,  H01L21/768 ,  H01L21/311 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/845 ,  H01L23/485 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/785

Abstract: A method for fabricating a finFET integrated circuit includes providing a finFET integrated circuit structure including a fin structure, a replacement metal gate structure having a silicon nitride cap disposed over and in contact with the fin structure, a contact structure including a tungsten material also disposed over and in contact with the fin structure, and an insulating layer disposed over the replacement metal gate structure and the contact structure. The method further includes forming a first opening in the insulating layer over the replacement gate structure and a second opening in the insulating layer over the contact structure. Forming the first and second openings includes exposing the FinFET integrated circuit structure to a single extreme ultraviolet lithography patterning. Still further, the method includes removing a portion of the silicon nitride material of the replacement metal gate structure and forming a metal fill material in the first and second openings.

Abstract translation: 一种用于制造finFET集成电路的方法包括提供finFET集成电路结构，其包括翅片结构，具有设置在翅片结构上并与翅片结构接触的氮化硅盖的替换金属栅极结构，包括钨材料的接触结构也布置在 并且与翅片结构接触，以及设置在替换金属栅极结构和接触结构之上的绝缘层。 所述方法还包括在所述绝缘层上形成位于所述替代栅极结构上的第一开口和在所述接触结构上的所述绝缘层中的第二开口。 形成第一和第二开口包括将FinFET集成电路结构暴露于单个极紫外光刻图案。 此外，该方法包括去除替代金属栅极结构的一部分氮化硅材料并在第一和第二开口中形成金属填充材料。

公开(公告)号：US20140183720A1

公开(公告)日：2014-07-03

申请号：US13731305

申请日：2012-12-31

Applicant: GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Scott Beasor ,  Jay Strane ,  Man Fai Ng ,  Brett H. Engel ,  Chang Yong Xiao ,  Michael P. Belyansky ,  Tsung-Liang Chen ,  Kyung Bum Koo

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L23/48 ,  H01L21/76832 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Methods of manufacturing semiconductor integrated circuits having a compressive nitride layer are disclosed. In one example, a method of fabricating an integrated circuit includes depositing an aluminum layer over a semiconductor substrate, depositing a tensile silicon nitride layer or a neutral silicon nitride layer over the aluminum layer, and depositing a compressive silicon nitride layer over the tensile silicon nitride layer or the neutral silicon nitride layer. The compressive silicon nitride layer is deposited at a thickness that is at least about twice a thickness of the tensile silicon nitride layer or the neutral silicon nitride layer. Further, there is no delamination present at an interface between the aluminum layer and the tensile silicon nitride layer or the neutral silicon nitride layer, or at an interface between tensile silicon nitride layer or the neutral silicon nitride layer and the compressive nitride layer.

Abstract translation: 公开了具有压缩氮化物层的半导体集成电路的制造方法。 在一个示例中，制造集成电路的方法包括在半导体衬底上沉积铝层，在铝层上沉积拉伸氮化硅层或中性氮化硅层，以及在抗拉氮化硅上沉积压缩氮化硅层 层或中性氮化硅层。 压缩氮化硅层以至少约为拉伸氮化硅层或中性氮化硅层厚度的约两倍的厚度沉积。 此外，在铝层和拉伸氮化硅层或中性氮化硅层之间的界面处，或者在拉伸氮化硅层或中性氮化硅层与压缩氮化物层之间的界面处没有分层存在。

公开(公告)号：US10832966B2

公开(公告)日：2020-11-10

申请号：US15899986

申请日：2018-02-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chang Seo Park ,  Haiting Wang ,  Shimpei Yamaguchi ,  Junsic Hong ,  Yong Mo Yang ,  Scott Beasor

IPC: H01L27/115 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

Abstract: Structures and fabrication methods for a field-effect transistor. First and second spacers are formed adjacent to opposite sidewalls of a gate structure. A section of the gate structure is partially removed with a first etching process to form a cut that extends partially through the gate structure. After partially removing the section of the gate structure with the first etching process, upper sections of the first and second sidewall spacers arranged above the gate structure inside the cut are at least partially removed. After at least partially removing the upper sections of the first and second sidewall spacers, the section of the gate structure is completely removed from the cut with a second etching process. A dielectric material is deposited inside the cut to form a dielectric pillar.

公开(公告)号：US10832839B1

公开(公告)日：2020-11-10

申请号：US16570575

申请日：2019-09-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Scott Beasor ,  Haiting Wang ,  Sipeng Gu ,  Jiehui Shu

IPC: H01C7/22 ,  H01C1/012 ,  H01C17/00 ,  H01L23/522 ,  H01L49/02

Abstract: Device structures and fabrication methods for an on-chip resistor. A dielectric layer includes a trench with a bottom and a sidewall arranged to surround the bottom. A metal layer is disposed on the dielectric layer at the sidewall of the trench. The metal layer includes a surface that terminates the metal layer at the bottom of the trench to define a discontinuity that extends along a length of the trench.

公开(公告)号：US10741556B2

公开(公告)日：2020-08-11

申请号：US15719014

申请日：2017-09-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George R. Mulfinger ,  Lakshmanan H. Vanamurthy ,  Scott Beasor ,  Timothy J. McArdle ,  Judson R. Holt ,  Hao Zhang

IPC: H01L27/092 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/165 ,  H01L21/02 ,  H01L29/167 ,  H01L21/285 ,  H01L29/66 ,  H01L21/265 ,  H01L29/45 ,  H01L23/485 ,  H01L21/768 ,  H01L29/417

Abstract: A method for forming a self-aligned sacrificial epitaxial cap for trench silicide and the resulting device are provided. Embodiments include a Si fin formed in a PFET region; a pair of Si fins formed in a NFET region; epitaxial S/D regions formed on ends of the Si fins; a replacement metal gate formed over the Si fins in the PFET and NFET regions; metal silicide trenches formed over the epitaxial S/D regions in the PFET and NEFT regions; a metal layer formed over top surfaces of the S/D region in the PFET region and top and bottom surfaces of the S/D regions in the NFET region, wherein the epitaxial S/D regions in the PFET and NFET regions are diamond shaped in cross-sectional view.