公开(公告)号：US09112032B1

公开(公告)日：2015-08-18

申请号：US14305457

申请日：2014-06-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bingwu Liu ,  Hui Zang

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L21/84 ,  H01L29/423

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66818

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin protection layer around a fin, forming a sacrificial gate electrode above a section of the fin protection layer, forming at least one sidewall spacer adjacent the sacrificial gate electrode, removing the sacrificial gate electrode to define a gate cavity that exposes a portion of the fin protection layer, oxidizing at least the exposed portion of the fin protection layer to thereby form an oxidized portion of the fin protection layer, and removing the oxidized portion of the fin protection layer so as to thereby expose a surface of the fin within the gate cavity.

Abstract translation: 本文公开的一种说明性方法包括在鳍周围形成翅片保护层，在翅片保护层的一部分上形成牺牲栅电极，形成邻近牺牲栅电极的至少一个侧壁间隔物，去除牺牲栅极 电极，以限定露出所述鳍片保护层的一部分的栅极腔，至少氧化所述鳍片保护层的暴露部分，从而形成所述鳍片保护层的氧化部分，以及去除所述鳍片保护层的氧化部分，从而 从而使得在门腔内的翅片的表面露出。

公开(公告)号：US20210020515A1

公开(公告)日：2021-01-21

申请号：US16515638

申请日：2019-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bingwu Liu ,  Tao Chu ,  Man Gu

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10

Abstract: One illustrative method disclosed herein includes forming at least one fin, forming a first recessed layer of insulating material adjacent the at least one fin and forming epi semiconductor material on the at least one fin. In this example, the method also includes forming a second recessed layer of insulating material above the first recessed layer of insulating material, wherein at least a portion of the epi semiconductor material is positioned above a level of the upper surface of the second recessed layer of insulating material, and forming a source/drain contact structure above the second recessed layer of insulating material, wherein the source/drain contact structure is conductively coupled to the epi semiconductor material.

公开(公告)号：US20200286790A1

公开(公告)日：2020-09-10

申请号：US16296469

申请日：2019-03-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hong ,  Hong Yu ,  Tao Chu ,  Bingwu Liu

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/308

Abstract: One illustrative method disclosed herein includes forming a conformal SMCM layer above a conformal high-k gate insulation layer within each of first and second replacement gate cavities (RGC), removing the SMCM layer from the first RGC while leaving the SMCM layer in position within the second RGC, forming a first conformal metal-containing material (MCM) layer above the gate insulation layer within the first RGC and above the SMCM layer in position within the second RGC, removing the first conformal MCM layer and the conformal SMCM layer positioned within the second RGC while leaving the first conformal MCM layer within the first RGC, and forming a second conformal MCM layer above the first conformal MCM layer positioned within the first RGC and above the gate insulation layer positioned within the second RGC.

公开(公告)号：US10276560B2

公开(公告)日：2019-04-30

申请号：US15638850

申请日：2017-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bingwu Liu ,  Hui Zang

IPC: H01L27/06 ,  H01L21/8234

Abstract: Structures for a passive device of an integrated circuits and associated fabrication methods. A semiconductor substrate having raised fins and an dielectric isolation layer between the fins is formed. An etch stop layer is formed over the dielectric isolation layer between fins of a passive device. An interlayer dielectric layer is formed over the fins and etch stop layer. The interlayer dielectric layer is selectively etched to form an opening for conductive contact to the fins, where the etch stop layer prevents etching of the dielectric isolation layer. A conductive contact is formed to contact the plurality of fins, with the conductive contact terminating at the etch stop layer.

公开(公告)号：US09564484B2

公开(公告)日：2017-02-07

申请号：US14983157

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Bingwu Liu

IPC: H01L21/02 ,  H01L49/02 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide improved metal-insulator-metal (MIM) capacitors. In embodiments, series resistance is reduced by forming a via underneath the bottom plate of a MIM capacitor, leading to a metallization layer or intermediate metal sublayer. In embodiments, the MIM capacitor is formed with a corrugated shape to increase the plate surface area, allowing a thicker dielectric to be used, thereby mitigating leakage issues.

Abstract translation: 本发明的实施例提供改进的金属 - 绝缘体 - 金属（MIM）电容器。 在实施例中，通过在MIM电容器的底板下面形成通孔，导致金属化层或中间金属子层来减小串联电阻。 在实施例中，MIM电容器形成为波纹形状以增加板表面积，允许使用更厚的电介质，从而减轻漏电问题。

公开(公告)号：US09425129B1

公开(公告)日：2016-08-23

申请号：US14789160

申请日：2015-07-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Bingwu Liu ,  Dingyou Zhang

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/528 ,  H01L29/16 ,  H01L29/161 ,  H01L21/02

CPC classification number: H01L23/481 ,  H01L21/76831 ,  H01L21/76898 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165

Abstract: Methods and structures for fabricating conductive vias in circuit structures are provided. Methods may include, for example, providing a substrate that includes a dopant and at least one trench formed in the substrate; providing an undoped semiconductor layer over a surface of the substrate within the trench; and providing a conductive material on top of dielectric layer in the trench, the conductive material forming the conductive via. The undoped semiconductor layer, having no dopant, reduces a parasitic capacitance between the conductive via and the substrate. The undoped semiconductor layer may also prevent migration of dopant from the substrate into the undoped semiconductor layer, further reducing capacitance in the circuit structure.

Abstract translation: 提供了在电路结构中制造导电通孔的方法和结构。 方法可以包括例如提供包括掺杂剂的衬底和在衬底中形成的至少一个沟槽; 在所述沟槽内的所述衬底的表面上提供未掺杂的半导体层; 并且在沟槽中的电介质层的顶部提供导电材料，导电材料形成导电通孔。 没有掺杂剂的未掺杂的半导体层降低了导电通孔和衬底之间的寄生电容。 未掺杂的半导体层还可以防止掺杂剂从衬底迁移到未掺杂的半导体层中，进一步降低电路结构中的电容。

公开(公告)号：US09171922B1

公开(公告)日：2015-10-27

申请号：US14329263

申请日：2014-07-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Bingwu Liu

IPC: H01L27/01 ,  H01L21/338 ,  H01L29/423 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L27/0688 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: One illustrative device disclosed herein includes, among other things, an active layer positioned above a layer of insulating material, a fin positioned above the active layer, a gate insulation layer positioned on the active layer and on the fin, a conductive gate structure that is positioned around at least a portion of the fin and above at least a portion of the active layer, wherein the conductive gate structure comprises at least one work function adjusting metal layer positioned on the gate insulation layer, a first channel region defined in the fin under the conductive gate structure, and a second channel region defined in the active layer under the conductive gate structure.

Abstract translation: 本文公开的一个说明性装置尤其包括位于绝缘材料层之上的有源层，位于有源层上方的鳍，位于有源层上和鳍上的栅绝缘层，导电栅结构， 定位在所述鳍片的至少一部分上方和所述有源层的至少一部分之上，其中所述导电栅极结构包括位于所述栅极绝缘层上的至少一个功函数调整金属层，限定在所述鳍下的第一沟道区域 所述导电栅极结构以及在所述有源层中限定在所述导电栅极结构之下的第二沟道区。

公开(公告)号：US20150091097A1

公开(公告)日：2015-04-02

申请号：US14043871

申请日：2013-10-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Bingwu Liu ,  Randy Mann

IPC: H01L27/11 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/265

CPC classification number: H01L27/1104 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823431 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/66803 ,  H01L29/785

Abstract: Approaches for providing a hardmask used during a halo/extension implant of a static random access memory (SRAM) layout for a semiconductor device are disclosed. Specifically, approaches are provided for forming a pull-down (PD) transistor over a substrate; forming a pass-gate (PG) transistor over the substrate; and patterning a hardmask over the device, the hardmask including a first section adjacent the PD transistor and a second section adjacent the PG transistor, wherein a distance between the first section and the PD transistor is shorter than a distance between the second section and the PG transistor. The respective distances between the first section and the PD transistor, and the second section and the PG transistor, are selected to prevent a halo/extension implant from impacting one side of the PD transistor, while allowing the halo/extension implant to impact both sides of the PG transistor.

Abstract translation: 公开了用于提供在半导体器件的静态随机存取存储器（SRAM）布局的晕圈/扩展注入期间使用的硬掩模的方法。 具体地，提供了用于在衬底上形成下拉（PD）晶体管的方法; 在衬底上形成栅极（PG）晶体管; 以及在所述器件上构图硬掩模，所述硬掩模包括与所述PD晶体管相邻的第一部分和与所述PG晶体管相邻的第二部分，其中所述第一部分与所述PD晶体管之间的距离小于所述第二部分与所述PG之间的距离 晶体管。 选择第一部分和PD晶体管以及第二部分和PG晶体管之间的相应距离以防止光晕/延伸注入物撞击PD晶体管的一侧，同时允许光晕/延伸植入物撞击两侧 的PG晶体管。

公开(公告)号：US10553707B1

公开(公告)日：2020-02-04

申请号：US16108152

申请日：2018-08-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanping Shen ,  Hui Zang ,  Bingwu Liu ,  Manoj Joshi ,  Jae Gon Lee ,  Hsien-Ching Lo ,  Zhaoying Hu

IPC: H01L29/66 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/78

Abstract: Methods form devices by patterning a lower layer to form a fin, and forming a sacrificial gate along sidewalls of the fin. Such methods form a mask with cut openings on the sacrificial gate and remove sections of the fin and the sacrificial gate exposed through the cut openings to divide the fin into fin portions and create cut areas between the fin portions. Additionally, these methods remove the mask, epitaxially grow source/drains in the cut areas, replace the sacrificial gate with a gate conductor, and form a gate contact on the gate conductor over a center of the fin portions.

公开(公告)号：US10177151B1

公开(公告)日：2019-01-08

申请号：US15632702

申请日：2017-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanzhen Wang ,  Hui Zang ,  Bingwu Liu

IPC: H01L23/535 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/66

Abstract: A method and structure for a semiconductor device that includes one or more fin-type field effect transistors (FINFETs) and single-diffusion break (SDB) type isolation regions, which are within a semiconductor fin and define the active device region(s) for the FINFET(s). Asymmetric trenches are formed in a substrate through asymmetric cuts in sacrificial fins formed on the substrate. The asymmetric cuts have relatively larger gaps between fin portions that are closest to the substrate, and deeper portions of the asymmetric trenches are relatively wider than shallower portions. Channel regions are formed in the substrate below two adjacent fins. Source/drain regions of complementary transistors are formed in the substrate on opposite sides of the channel regions. The asymmetric trenches are filled with an insulator to form a single-diffusion break between two source/drain regions of different ones of the complementary transistors. Also disclosed is a semiconductor structure formed according to the method.