公开(公告)号：US10825897B2

公开(公告)日：2020-11-03

申请号：US16262052

申请日：2019-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hong ,  George R. Mulfinger ,  Hui Zang ,  Liu Jiang ,  Zhenyu Hu

IPC: H01L29/08 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/786 ,  H01L29/78 ,  H01L21/28

Abstract: One illustrative method disclosed herein may include forming a first straight sidewall spacer adjacent a gate structure of a transistor, forming a recessed layer of sacrificial material adjacent the first straight sidewall spacer and forming a second straight sidewall spacer on a portion of the outer surface of the first straight sidewall spacer and above the recessed layer of sacrificial material. The method may also include removing the recessed layer of sacrificial material so as to expose a first vertical portion of the outer surface of the first straight sidewall spacer and forming an epi material on and above the substrate, wherein an edge of the epi material engages the first straight sidewall spacer.

公开(公告)号：US10811422B2

公开(公告)日：2020-10-20

申请号：US16196060

申请日：2018-11-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanping Shen ,  Wei Hong ,  Hui Zang ,  David P. Brunco

IPC: H01L27/11 ,  H01L29/78 ,  H01L29/08

Abstract: Methods according to the disclosure include forming a mask over a substrate to cover a first semiconductor region on the substrate and a first gate structure on the first semiconductor region. The second semiconductor region may be recessed from an initial height above the substrate to a reduced height above the substrate. The mask may be removed before forming a plurality of cavities by etching the first and second semiconductor regions, the plurality of cavities including a first cavity having a first depth within the first semiconductor region and a second cavity having a second depth within the second semiconductor region, wherein the second depth is greater than the first depth. The method also may include forming a plurality of epitaxial regions within the plurality of cavities.

公开(公告)号：US10784342B1

公开(公告)日：2020-09-22

申请号：US16385197

申请日：2019-04-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hong ,  Hong Yu ,  Jianwei Peng ,  Hui Zhan

IPC: H01L29/06 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/66

Abstract: Structures that include a single diffusion break and methods of forming a single diffusion break. A source/drain region is arranged inside a first cavity in a semiconductor fin, and a dielectric layer is arranged inside a second cavity in the semiconductor fin. A liner, which is composed of a dielectric material, includes a section that is arranged inside the second cavity laterally between the dielectric layer and the source/drain region.

公开(公告)号：US20200286790A1

公开(公告)日：2020-09-10

申请号：US16296469

申请日：2019-03-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hong ,  Hong Yu ,  Tao Chu ,  Bingwu Liu

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/308

Abstract: One illustrative method disclosed herein includes forming a conformal SMCM layer above a conformal high-k gate insulation layer within each of first and second replacement gate cavities (RGC), removing the SMCM layer from the first RGC while leaving the SMCM layer in position within the second RGC, forming a first conformal metal-containing material (MCM) layer above the gate insulation layer within the first RGC and above the SMCM layer in position within the second RGC, removing the first conformal MCM layer and the conformal SMCM layer positioned within the second RGC while leaving the first conformal MCM layer within the first RGC, and forming a second conformal MCM layer above the first conformal MCM layer positioned within the first RGC and above the gate insulation layer positioned within the second RGC.

公开(公告)号：US10714577B2

公开(公告)日：2020-07-14

申请号：US16149711

申请日：2018-10-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hong ,  Hui Zang ,  Hsien-Ching Lo

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L27/12 ,  H01L29/51 ,  H01L29/49 ,  H01L29/165 ,  H01L29/78 ,  H01L21/84 ,  H01L21/02 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/027 ,  H01L21/28 ,  H01L21/285 ,  H01L29/66

Abstract: Structures for a field-effect transistor and methods for fabricating a structure for a field-effect transistor. First and second device structure are respectively formed in first and second device regions, and a first dielectric layer is formed over the first and second device regions. The first dielectric layer includes a recess defining a step at a transition between the first and second device regions, and a second dielectric layer is arranged within the recess in the first dielectric layer. A third dielectric layer is arranged over the first dielectric layer in the first device region and over the second dielectric layer in the second device region. A contact, which is coupled with the second device structure, extends through the first, second, and third dielectric layers in the second device region.

公开(公告)号：US20200161315A1

公开(公告)日：2020-05-21

申请号：US16196060

申请日：2018-11-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanping Shen ,  Wei Hong ,  Hui Zang ,  David P. Brunco

IPC: H01L27/11

Abstract: Methods according to the disclosure include forming a mask over a substrate to cover a first semiconductor region on the substrate and a first gate structure on the first semiconductor region. The second semiconductor region may be recessed from an initial height above the substrate to a reduced height above the substrate. The mask may be removed before forming a plurality of cavities by etching the first and second semiconductor regions, the plurality of cavities including a first cavity having a first depth within the first semiconductor region and a second cavity having a second depth within the second semiconductor region, wherein the second depth is greater than the first depth. The method also may include forming a plurality of epitaxial regions within the plurality of cavities.

公开(公告)号：US20190148492A1

公开(公告)日：2019-05-16

申请号：US15811990

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yoong Hooi Yong ,  Yanping Shen ,  Hsien-Ching Lo ,  Xusheng Wu ,  Joo Tat Ong ,  Wei Hong ,  Yi Qi ,  Dongil Choi ,  Yongjun Shi ,  Alina Vinslava ,  James Psillas ,  Hui Zang

IPC: H01L29/08 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02

CPC classification number: H01L29/0847 ,  H01L21/02576 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/7848

Abstract: A semiconductor structure including a source/drain region is disclosed. The source/drain region may include a first epitaxial region along at least one sidewall of the source/drain region having a substantially uniform sidewall thickness. The semiconductor structure may further include a gate structure adjacent and above the source/drain region wherein at least a portion of the first epitaxial region is positioned below a sidewall spacer of the gate structure. A method of forming a source/drain region including a first epitaxial region having a substantially uniform sidewall thickness is disclosed. The method may include forming a trench in a substrate adjacent to a gate structure, forming the first epitaxial region in the trench, forming a spacer material layer on the gate structure and on a portion of the first epitaxial region, and removing a portion of the first epitaxial region using the spacer material layer as a mask.

公开(公告)号：US10777642B2

公开(公告)日：2020-09-15

申请号：US16262105

申请日：2019-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hong ,  George R. Mulfinger ,  Hui Zang ,  Liu Jiang ,  Zhenyu Hu

IPC: H01L29/08 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

Abstract: One illustrative method disclosed herein may include forming a first straight sidewall spacer adjacent a gate structure of a transistor, forming a second straight sidewall spacer on the first straight sidewall spacer and forming a recessed layer of sacrificial material adjacent the second straight sidewall spacer such that the recessed layer of sacrificial material covers an outer surface of a first vertical portion of the second straight sidewall spacer while exposing a second vertical portion of the second straight sidewall spacer. In this example, the method may also include removing the second vertical portion of the second straight sidewall spacer, removing the recessed layer of sacrificial material and forming an epi material such that an edge of the epi material engages the outer surface of the first vertical portion of the second straight sidewall spacer.

公开(公告)号：US20200243646A1

公开(公告)日：2020-07-30

申请号：US16262105

申请日：2019-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hong ,  George R. Mulfinger ,  Hui Zang ,  Liu Jiang ,  Zhenyu Hu

IPC: H01L29/08 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78

Abstract: One illustrative method disclosed herein may include forming a first straight sidewall spacer adjacent a gate structure of a transistor, forming a second straight sidewall spacer on the first straight sidewall spacer and forming a recessed layer of sacrificial material adjacent the second straight sidewall spacer such that the recessed layer of sacrificial material covers an outer surface of a first vertical portion of the second straight sidewall spacer while exposing a second vertical portion of the second straight sidewall spacer. In this example, the method may also include removing the second vertical portion of the second straight sidewall spacer, removing the recessed layer of sacrificial material and forming an epi material such that an edge of the epi material engages the outer surface of the first vertical portion of the second straight sidewall spacer.

公开(公告)号：US10700173B2

公开(公告)日：2020-06-30

申请号：US15949730

申请日：2018-04-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Hsien-Ching Lo ,  Hong Yu ,  Yanping Shen ,  Wei Hong ,  Xing Zhang ,  Ruilong Xie ,  Haiting Wang ,  Hui Zhan ,  Yong Jun Shi

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/45 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/165

Abstract: One illustrative FinFET device disclosed herein includes a source/drain structure that, when viewed in a cross-section taken through the fin in a direction corresponding to the gate width (GW) direction of the device, comprises a perimeter and a bottom surface. The source/drain structure also has an axial length that extends in a direction corresponding to the gate length (GL) direction of the device. The device also includes a metal silicide material positioned on at least a portion of the perimeter of the source/drain structure for at least a portion of the axial length of the source/drain structure and on at least a portion of the bottom surface of the source/drain structure for at least a portion of the axial length of the source/drain structure.