公开(公告)号：US08753940B1

公开(公告)日：2014-06-17

申请号：US13834410

申请日：2013-03-15

Applicant: Globalfoundries Inc.

Inventor： Andy C. Wei ,  Dae Geun Yang

IPC: H01L21/336

CPC classification number: H01L21/845 ,  H01L21/823431

Abstract: One method includes forming a plurality of trenches in a semiconducting substrate to define a plurality of fins, forming a layer of overfill material that overfills the trenches, wherein an upper surface of the overfill material is positioned above an upper surface of the fins, forming a masking layer above the layer of overfill material, wherein the masking layer has an opening that is positioned above a subset of the plurality of fins that is desired to be removed and wherein the subset of fins is comprised of at least one but less than all of the fins, performing an etching process through the masking layer to remove at least a portion of the layer of overfill material and expose the upper surface of the subset of fins, and performing a second etching process on the exposed surface of the subset of fins to remove the subset of fins.

Abstract translation: 一种方法包括在半导体衬底中形成多个沟槽以限定多个翅片，形成覆盖沟槽的填充材料层，其中，所述填充材料的上表面位于所述翅片的上表面上方，形成 掩蔽层，其中所述掩蔽层具有位于所述多个翅片的子集上方的开口，所述多个翅片的子集需要被去除，并且其中所述翅片的子集包括至少一个但不是全部的 翅片，通过掩模层进行蚀刻工艺，以去除覆盖层材料层的至少一部分，并暴露散热片子组的上表面，并对翅片子组的暴露表面进行第二蚀刻工艺，以 去除鳍片的子集。

公开(公告)号：US09735154B2

公开(公告)日：2017-08-15

申请号：US14918012

申请日：2015-10-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Dae-han Choi ,  Dae Geun Yang ,  Xiang Hu ,  Mariappan Hariharaputhiran

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/308 ,  H01L21/311 ,  H01L21/306 ,  H01L21/762 ,  H01L21/033 ,  H01L21/475 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/475 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/785

Abstract: Embodiments of the present invention provide methods of removing fin portions from a finFET. At a starting point, a high-K dielectric layer is disposed on a substrate. A fin hardmask and lithography stack is deposited on the high-k dielectric. A fin hardmask is exposed, and a first portion of the fin hardmark is removed. The lithography stack is removed. A second portion of the fin hardmask is removed. Fins are formed. A gap fill dielectric is deposited and recessed.

公开(公告)号：US20150279684A1

公开(公告)日：2015-10-01

申请号：US14225542

申请日：2014-03-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andy Chih-Hung Wei ,  Dae-han Choi ,  Dae Geun Yang ,  Xiang Hu ,  Mariappan Hariharaputhiran

IPC: H01L21/308 ,  H01L29/66 ,  H01L21/762 ,  H01L21/311 ,  H01L21/306

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/475 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/785

Abstract: Embodiments of the present invention provide methods of removing fin portions from a finFET. At a starting point, a high-K dielectric layer is disposed on a substrate. A fin hardmask and lithography stack is deposited on the high-k dielectric. A fin hardmask is exposed, and a first portion of the fin hardmark is removed. The lithography stack is removed. A second portion of the fin hardmask is removed. Fins are formed. A gap fill dielectric is deposited and recessed.

Abstract translation: 本发明的实施例提供了从finFET去除翅片部分的方法。 在起始点，高K电介质层设置在基板上。 翅片硬掩模和光刻叠层沉积在高k电介质上。 翅片硬掩模被暴露，并且鳍状硬标记的第一部分被去除。 去除光刻叠层。 拆下散热片硬掩模的第二部分。 鳍形成。 间隙填充电介质被沉积并凹进。

公开(公告)号：US08993445B2

公开(公告)日：2015-03-31

申请号：US13740343

申请日：2013-01-14

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Dae-Han Choi ,  Dae Geun Yang ,  Chang Ho Maeng ,  Wontae Hwang

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/311 ,  B44C1/22 ,  C25F3/00 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01L29/40

CPC classification number: H01L29/401 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods are provided for facilitating fabricating a semiconductor device by selectively etching a gate structure sidewall(s) to facilitate subsequent sidewall spacer isolation. The method includes, for instance: providing a gate structure with a protective layer(s) over the gate structure, the gate structure including one or more sidewalls; selectively removing a portion of the gate structure along at least one sidewall to partially undercut the protective layer(s); and forming a sidewall spacer(s) over the sidewall(s) of the gate structure, with a portion of the sidewall spacer at least partially filling the partial undercut of the protective layer(s), and residing below the protective layer(s). In certain embodiments, the selectively removing includes implanting the sidewall(s) with a dopant to produce a doped region(s) of the gate structure, and subsequently, at least partially removing the doped region(s) of the gate structure selective to an undoped region of the gate structure.

Abstract translation: 提供了通过选择性地蚀刻栅极结构侧壁以促进随后的侧壁间隔隔离来促进制造半导体器件的方法。 该方法包括例如：在栅极结构上提供具有保护层的栅极结构，栅极结构包括一个或多个侧壁; 沿着至少一个侧壁选择性地去除所述栅极结构的一部分以部分地切割所述保护层; 以及在所述栅极结构的侧壁上形成侧壁间隔物，所述侧壁间隔物的一部分至少部分地填充所述保护层的部分底切，并且位于所述保护层的下方， 。 在某些实施例中，选择性去除包括用掺杂剂注入侧壁以产生栅极结构的掺杂区域，并且随后至少部分地去除栅极结构的掺杂区域， 栅极结构的未掺杂区域。

公开(公告)号：US20140148011A1

公开(公告)日：2014-05-29

申请号：US13688258

申请日：2012-11-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dae-han Choi ,  Dae Geun Yang ,  Chang Ho Maeng

IPC: H01L21/3065

CPC classification number: H01L21/3065 ,  H01L21/3083 ,  H01L29/66795

Abstract: An improved method of forming semiconductor fins is disclosed. Cavities are formed by etching a semiconductor substrate to a first depth. A surface treatment layer such as a nitride layer is then deposited or formed on the interior surface of the cavities. The etch then continues deeper, while the surface treatment layer protects the upper portion of the cavities.

Abstract translation: 公开了一种形成半导体鳍片的改进方法。 通过将半导体衬底蚀刻到第一深度来形成空穴。 然后在空腔的内表面上沉积或形成诸如氮化物层的表面处理层。 然后蚀刻继续更深，同时表面处理层保护空腔的上部。

公开(公告)号：US08697501B1

公开(公告)日：2014-04-15

申请号：US13693094

申请日：2012-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dae-han Choi ,  Dae Geun Yang

IPC: H01L21/00

CPC classification number: H01L29/66795 ,  H01L29/66545

Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device (e.g., FinFET device) having a gate structure formed on a planar surface thereof. Specifically, a uniform, oxide-fin (OF) surface is formed. Then, a “dummy” gate structure and a set of spacers are formed thereon. Once the gate structure and set of spacers have been formed, the OF surface may be recessed. In one embodiment, the OF surface is uniformly recessed. In another embodiment, the OF surface is selectively recessed to yield a set of fins. In any event, after the recessing, an epitaxial layer is grown and an oxide fill is performed. Then, the “dummy” gate structure is removed (from between the set of spacers) and an oxide recess is performed to yield a set of channel fins between the spacers.

Abstract translation: 本发明的方面通常涉及用于形成其平面上形成有栅极结构的半导体器件（例如，FinFET器件）的方法。 具体地，形成均匀的氧化物翅片（OF）表面。 然后，在其上形成“虚拟”栅极结构和一组间隔物。 一旦形成了栅极结构和间隔物组，则OF表面可以是凹进的。 在一个实施例中，OF表面是均匀凹陷的。 在另一个实施例中，OF表面选择性地凹入以产生一组翅片。 无论如何，在凹陷之后，生长外延层并进行氧化物填充。 然后，从“间隔件组”之间移除“虚拟”门结构，并且执行氧化物凹槽以产生间隔件之间的一组通道散热片。