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    PARTIALLY CRYSTALLIZED FIN HARD MASK FOR FIN FIELD-EFFECT-TRANSISTOR (FINFET) DEVICE
    3.
    发明申请
    PARTIALLY CRYSTALLIZED FIN HARD MASK FOR FIN FIELD-EFFECT-TRANSISTOR (FINFET) DEVICE 审中-公开
    FIN场效应晶体管（FINFET）器件的部分晶体结构硬掩模

    公开(公告)号：US20150270175A1

    公开(公告)日：2015-09-24

    申请号：US14219059

    申请日：2014-03-19

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xiang Hu ,  Andy Chih-Hung Wei ,  Dae-han Choi ,  Mariappan Hariharaputhiran ,  Weihua Tong ,  Dae Geun Yang ,  Akshey Sehgal ,  Jing Wan

    IPC: H01L21/8234 ,  H01L21/027 ,  H01L21/306 ,  H01L21/324 ,  H01L29/78 ,  H01L21/308

    CPC classification number: H01L21/823431 ,  H01L21/268 ,  H01L21/3081 ,  H01L21/3086 ,  H01L29/66795

    Abstract: Provided herein are approaches for forming a fin field-effect-transistor (FinFET) device using a partially crystallized fin hard mask. Specifically, a hard mask is patterned over a substrate, and the FinFET device is annealed to form a set of crystallized hard mask elements adjacent a set of non-crystallized hard mask elements. A masking structure is provided over a first section of the patterned hard mask to prevent the set of non-crystallized hard mask elements from being crystallized during the anneal. During a subsequent fin cut process, the non-crystallized mask elements are removed, while crystallized mask elements remain. A set of fins is then formed in the FinFET device according to the location(s) of the crystallized mask elements.

    Abstract translation: 本文提供了使用部分结晶的翅片硬掩模形成鳍状场效应晶体管（FinFET）器件的方法。 具体地说，将硬掩模图案化在衬底上，并且FinFET器件被退火以形成与一组非结晶硬掩模元件相邻的一组结晶的硬掩模元件。 在图案化的硬掩模的第一部分上提供掩模结构，以防止在退火期间该组非结晶硬掩模元件结晶。 在随后的翅片切割过程中，除去未结晶的掩模元件，同时保留结晶的掩模元件。 然后根据结晶化掩模元件的位置在FinFET器件中形成一组翅片。

    Devices and methods of forming fins at tight fin pitches
    5.
    发明授权
    Devices and methods of forming fins at tight fin pitches 有权
    在紧凑的翅片间距处形成翅片的装置和方法

    公开(公告)号：US09105478B2

    公开(公告)日：2015-08-11

    申请号：US14064840

    申请日：2013-10-28

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Andy Wei ,  Mariappan Hariharaputhiran ,  Dae Geun Yang ,  Dae-Han Choi ,  Xiang Hu ,  Richard J. Carter ,  Akshey Sehgal

    IPC: H01L21/302 ,  H01L21/033 ,  G03F1/50

    CPC classification number: H01L21/0332 ,  G03F1/50 ,  H01L21/0276 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/823821 ,  H01L29/785

    Abstract: Devices and methods for forming semiconductor devices with fins at tight fin pitches are provided. One method includes, for instance: obtaining an intermediate semiconductor device; growing an epi layer over the substrate; forming a doped layer below the epi layer; depositing a first oxide layer on the epi layer; applying a dielectric material on the first oxide layer; and depositing a lithography stack on the dielectric material. One intermediate semiconductor device includes, for instance: a substrate with at least one n-well region and at least one p-well region; a doped layer over the substrate; an epi layer over the doped layer; a first oxide layer over the epi layer; a dielectric layer over the first oxide layer; and a lithography stack over the dielectric layer.

    Abstract translation: 提供了用于以紧密翅片间距形成翅片的半导体器件的装置和方法。 一种方法包括，例如：获得中间半导体器件; 在衬底上生长表层; 在外延层下方形成掺杂层; 在外延层上沉积第一氧化物层; 在第一氧化物层上施加电介质材料; 以及在介电材料上沉积光刻叠层。 一个中间半导体器件包括例如：具有至少一个n阱区和至少一个p阱区的衬底; 衬底上的掺杂层; 掺杂层上的外延层; 在epi层上的第一氧化物层; 第一氧化物层上的介电层; 以及介电层上的光刻叠层。

    METAL GATE STRUCTURE AND METHOD OF FORMATION
    7.
    发明申请
    METAL GATE STRUCTURE AND METHOD OF FORMATION 有权
    金属门结构和形成方法

    公开(公告)号：US20150340461A1

    公开(公告)日：2015-11-26

    申请号：US14282257

    申请日：2014-05-20

    Applicant: GLOBALFOUNDRIES Inc

    Inventor： Andy Chih-Hung Wei ,  Dae G. Yang ,  Mariappan Hariharaputhiran ,  Jing Wan

    IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78

    CPC classification number: H01L29/785 ,  H01L21/28247 ,  H01L27/1104 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/66795

    Abstract: Embodiments of the present invention provide a metal gate structure and method of formation. In the replacement metal gate (RMG) process flow, the gate cut process is performed after the metal gate is formed. This allows for a reduced margin between the end of the gate and an adjacent fin. It enables a thinner sacrificial layer on top of the dummy gate, since the gate cut step is deferred. The thinner sacrificial layer improves device quality by reducing the adverse effect of shadowing during implantation. Furthermore, in this process flow, the work function metal layer is terminated along the semiconductor substrate by a capping layer, which reduces undesirable shifts in threshold voltage that occurred in prior methods and structures.

    Abstract translation: 本发明的实施例提供一种金属栅极结构和形成方法。 在替代金属栅极（RMG）工艺流程中，栅极切割工艺在金属栅极形成之后进行。 这允许在门的末端和相邻鳍之间减小边缘。 它能够在虚拟栅极顶部形成更薄的牺牲层，因为栅极切割步骤被推迟。 更薄的牺牲层通过减少植入期间阴影的不利影响来提高器件质量。 此外，在该工艺流程中，功函数金属层通过封盖层沿着半导体衬底终止，这降低了在现有方法和结构中发生的阈值电压的不期望的移动。

    Devices and methods of forming finFETs with self aligned fin formation
    8.
    发明授权
    Devices and methods of forming finFETs with self aligned fin formation 有权
    具有自对准翅片形成的finFET的器件和方法

    公开(公告)号：US09147696B2

    公开(公告)日：2015-09-29

    申请号：US14043243

    申请日：2013-10-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jing Wan ,  Andy Wei ,  Lun Zhao ,  Dae Geun Yang ,  Jin Ping Liu ,  Tien-Ying Luo ,  Guillaume Bouche ,  Mariappan Hariharaputhiran ,  Churamani Gaire

    IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84

    CPC classification number: H01L27/0924 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.

    Abstract translation: 提供了用FinFET形成半导体器件的器件和方法。 一种方法包括例如：获得具有衬底和至少一个浅沟槽隔离区域的中间半导体器件; 在中间半导体器件上沉积硬掩模层; 蚀刻硬掩模层以形成至少一个翅片硬掩模; 以及在所述至少一个翅片硬掩模和所述基底的至少一部分上沉积至少一个牺牲栅极结构。 一个中间半导体器件包括例如：具有至少一个浅沟槽隔离区域的衬底; 在衬底上的至少一个翅片硬掩模; 至少一个翅片硬掩模上的至少一个牺牲栅极结构; 设置在所述至少一个牺牲栅极结构上的至少一个间隔物; 以及至少一个pFET区域和至少一个生长到衬底中的nFET区域。

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