公开(公告)号：US10727067B2

公开(公告)日：2020-07-28

申请号：US16203816

申请日：2018-11-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  David P. Brunco

IPC: H01L21/28 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/3213 ,  H01L27/088 ,  H01L29/49

Abstract: Methods of forming a structure that includes a field-effect transistor and structures that include a field effect-transistor. A cut is formed that extends through a gate structure of the field-effect transistor such that a gate electrode of the gate structure is divided into a first section having a first surface and a second section having a second surface spaced across the cut from the first surface. After forming the cut, a first section of a conductive layer is selectively deposited on the first surface of the first section of the gate electrode and a second section of the conductive layer is selectively deposited on the second surface of the second section of the gate electrode to shorten the cut. A dielectric material is deposited in the cut between the first and second sections of the conductive layer on the first and second surfaces of the gate electrode to form a dielectric pillar.

公开(公告)号：US20200161315A1

公开(公告)日：2020-05-21

申请号：US16196060

申请日：2018-11-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanping Shen ,  Wei Hong ,  Hui Zang ,  David P. Brunco

IPC: H01L27/11

Abstract: Methods according to the disclosure include forming a mask over a substrate to cover a first semiconductor region on the substrate and a first gate structure on the first semiconductor region. The second semiconductor region may be recessed from an initial height above the substrate to a reduced height above the substrate. The mask may be removed before forming a plurality of cavities by etching the first and second semiconductor regions, the plurality of cavities including a first cavity having a first depth within the first semiconductor region and a second cavity having a second depth within the second semiconductor region, wherein the second depth is greater than the first depth. The method also may include forming a plurality of epitaxial regions within the plurality of cavities.

公开(公告)号：US20190131177A1

公开(公告)日：2019-05-02

申请号：US15794600

申请日：2017-10-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David P. Brunco ,  Wei Zhao ,  Haiting Wang

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H01L29/06 ,  H01L21/306 ,  H01L27/088

Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. A plurality of sacrificial layers are formed on a dielectric layer. An opening is formed that includes a first section that extends through the sacrificial layers and a second section that extends through the dielectric layer. A semiconductor material is epitaxially grown inside the opening to form a fin. The first section of the opening has a first width dimension, and the second section of the opening has a second width dimension that is less than the first width dimension.

公开(公告)号：US20150340500A1

公开(公告)日：2015-11-26

申请号：US14282463

申请日：2014-05-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David P. Brunco

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/265 ,  H01L21/762

CPC classification number: H01L21/823412 ,  H01L21/0245 ,  H01L21/02499 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/7849

Abstract: Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is disposed on a semiconductor substrate. A silicon region and silicon germanium region are disposed adjacent to each other on the strain relaxed buffer. An additional region of silicon or silicon germanium provides quantum well isolation.

Abstract translation: 本发明的实施方案提供了具有应变松弛缓冲液的半导体结构及其制造方法。 应变松弛缓冲器设置在半导体衬底上。 在应变缓和缓冲器上，硅区域和硅锗区域彼此相邻设置。 硅或硅锗的附加区域提供量子阱隔离。

公开(公告)号：US20200176258A1

公开(公告)日：2020-06-04

申请号：US16203816

申请日：2018-11-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  David P. Brunco

IPC: H01L21/28 ,  H01L21/8234 ,  H01L21/3213 ,  H01L27/088 ,  H01L29/49 ,  H01L29/06

Abstract: Methods of forming a structure that includes a field-effect transistor and structures that include a field effect-transistor. A cut is formed that extends through a gate structure of the field-effect transistor such that a gate electrode of the gate structure is divided into a first section having a first surface and a second section having a second surface spaced across the cut from the first surface. After forming the cut, a first section of a conductive layer is selectively deposited on the first surface of the first section of the gate electrode and a second section of the conductive layer is selectively deposited on the second surface of the second section of the gate electrode to shorten the cut. A dielectric material is deposited in the cut between the first and second sections of the conductive layer on the first and second surfaces of the gate electrode to form a dielectric pillar.

公开(公告)号：US20190097019A1

公开(公告)日：2019-03-28

申请号：US15712748

申请日：2017-09-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Zhao ,  Haiting Wang ,  David P. Brunco ,  Jiehui Shu ,  Shesh Mani Pandey ,  Jinping Liu ,  Scott Beasor

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/417 ,  H01L21/762

CPC classification number: H01L29/6681 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/02664 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/41791 ,  H01L29/66795

Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.

公开(公告)号：US09953872B2

公开(公告)日：2018-04-24

申请号：US15699138

申请日：2017-09-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： David P. Brunco

IPC: H01L21/8238 ,  H01L21/31 ,  H01L21/469 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/266 ,  H01L21/02 ,  H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L29/165

CPC classification number: H01L21/823412 ,  H01L21/0245 ,  H01L21/02499 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/7849

Abstract: Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is disposed on a semiconductor substrate. A silicon region and silicon germanium region are disposed adjacent to each other on the strain relaxed buffer. An additional region of silicon or silicon germanium provides quantum well isolation.

公开(公告)号：US09257557B2

公开(公告)日：2016-02-09

申请号：US14282463

申请日：2014-05-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David P. Brunco

IPC: H01L21/8238 ,  H01L29/78 ,  H01L21/762 ,  H01L21/02 ,  H01L21/265

CPC classification number: H01L21/823412 ,  H01L21/0245 ,  H01L21/02499 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/7849

Abstract: Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is disposed on a semiconductor substrate. A silicon region and silicon germanium region are disposed adjacent to each other on the strain relaxed buffer. An additional region of silicon or silicon germanium provides quantum well isolation.

Abstract translation: 本发明的实施方案提供了具有应变松弛缓冲液的半导体结构及其制造方法。 应变松弛缓冲器设置在半导体衬底上。 在应变缓和缓冲器上，硅区域和硅锗区域彼此相邻设置。 硅或硅锗的附加区域提供量子阱隔离。

公开(公告)号：US20160035727A1

公开(公告)日：2016-02-04

申请号：US14446695

申请日：2014-07-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David P. Brunco

IPC: H01L27/092 ,  H01L29/161 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/36

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7848

Abstract: A CMOS structure with beneficial nMOS and pMOS band offsets is disclosed. A first silicon germanium layer is formed on a semiconductor substrate. A second silicon germanium layer is formed on the first silicon germanium layer. The second silicon germanium layer has a higher germanium percentage than the first silicon germanium layer. Furthermore, the germanium concentration of the two layers is selected such that there is a beneficial band offset for both N-type field effect transistors and P-type field effect transistors in a CMOS structure.

Abstract translation: 公开了具有有益的nMOS和pMOS带偏移的CMOS结构。 在半导体衬底上形成第一硅锗层。 在第一硅锗层上形成第二硅锗层。 第二硅锗层具有比第一硅锗层更高的锗百分比。 此外，选择两层的锗浓度，使得对于CMOS结构中的N型场效应晶体管和P型场效应晶体管都存在有益的带偏移。

公开(公告)号：US20140170839A1

公开(公告)日：2014-06-19

申请号：US13716758

申请日：2012-12-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： David P. Brunco

IPC: H01L29/66

CPC classification number: H01L29/66795 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66818

Abstract: One illustrative method disclosed herein includes forming a silicon/germanium fin in a layer of insulating material, wherein the fin has a first germanium concentration, recessing an upper surface of the layer of insulating material so as to expose a portion of the fin, performing an oxidation process so as to oxidize at least a portion of the fin and form a region in the exposed portion of the fin that has a second germanium concentration that is greater than the first germanium concentration, removing the oxide materials from the fin that was formed during the oxidation process and forming a gate structure that is positioned around at least the region having the second germanium concentration.

Abstract translation: 本文公开的一种说明性方法包括在绝缘材料层中形成硅/锗翅片，其中所述翅片具有第一锗浓度，使绝缘材料层的上表面凹陷以暴露所述鳍片的一部分，执行 氧化过程，以便氧化鳍片的至少一部分并在鳍的暴露部分中形成具有大于第一锗浓度的第二锗浓度的区域，从在第一锗浓度期间形成的翅片上除去氧化物材料 氧化工艺并形成位于至少具有第二锗浓度的区域周围的栅极结构。