公开(公告)号：US09391176B2

公开(公告)日：2016-07-12

申请号：US14522000

申请日：2014-10-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Ralf Richter ,  Peter Javorka

IPC: H01L25/00 ,  H01L29/06 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/165 ,  H01L25/065 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/66818 ,  H01L25/0657 ,  H01L29/0634 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78687 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides, in various aspects of the present disclosure, a semiconductor device which includes a semiconductor stack disposed over a surface of a substrate and a gate structure partially formed over an upper surface and two opposing sidewall surfaces of the semiconductor stack, wherein the semiconductor stack includes an alternating arrangement of at least two layers formed by a first semiconductor material and a second semiconductor material which is different from the first semiconductor material.

Abstract translation: 本公开在本公开的各个方面提供一种半导体器件，其包括设置在衬底的表面上的半导体堆叠和部分地形成在半导体堆叠的上表面和两个相对的侧壁表面上的栅极结构，其中， 半导体堆叠包括由第一半导体材料和与第一半导体材料不同的第二半导体材料形成的至少两层的交替布置。

公开(公告)号：US20160064510A1

公开(公告)日：2016-03-03

申请号：US14468839

申请日：2014-08-26

Applicant: GLOBALFOUNDRIES Inc. ,  Fraunhofer Gesellschaft zur Foerderung der angewandten Forschung e.V. ,  NaMLab gGmbH

Inventor： Johannes Mueller ,  Stefan Mueller ,  Stefan Flachowsky

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L27/11507 ,  H01L29/40111 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6684 ,  H01L29/78391

Abstract: An illustrative device disclosed herein includes a semiconductor substrate. The substrate includes a source region, a drain region and a channel region. The channel region is arranged between the source region and the drain region. A gate insulation layer is provided over the channel region. A floating gate electrode is provided over the gate insulation layer. A layer of a ferroelectric material is provided over the floating gate electrode. A top electrode is provided over the layer of ferroelectric material. A projected area of the top electrode onto a plane that is perpendicular to a thickness direction of the semiconductor substrate is smaller than a projected area of the floating gate electrode onto the plane.

Abstract translation: 本文公开的说明性器件包括半导体衬底。 衬底包括源极区，漏极区和沟道区。 沟道区域布置在源极区域和漏极区域之间。 栅极绝缘层设置在沟道区域的上方。 在栅绝缘层上设置浮栅电极。 在浮栅电极上设置铁电材料层。 顶层电极设置在铁电材料层上。 顶部电极在与半导体衬底的厚度方向垂直的平面上的投影面积小于浮动栅电极在平面上的投影面积。

公开(公告)号：US20160064123A1

公开(公告)日：2016-03-03

申请号：US14469012

申请日：2014-08-26

Applicant: Globalfoundries Inc.

Inventor： Stefan Flachowsky ,  Ralf Illgen ,  Jan Hoentschel

IPC: H01C1/16 ,  H01C17/075 ,  H01C7/18 ,  H01C7/00 ,  H01C7/02 ,  H01C7/04

CPC classification number: H01C1/16 ,  H01C7/008 ,  H01C7/021 ,  H01C7/027 ,  H01C7/041 ,  H01C17/075

Abstract: The present disclosure relates to a semiconductor structure comprising a positive temperature coefficient thermistor and a negative temperature coefficient thermistor, connected to each other in parallel by means of connecting elements which are configured such that the resistance resulting from the parallel connection is substantially stable in a predetermined temperature range, and to a corresponding manufacturing method.

Abstract translation: 本公开内容涉及包括正温度系数热敏电阻和负温度系数热敏电阻的半导体结构，该正温度系数热敏电阻和负温度系数热敏电阻通过连接元件彼此并联连接，连接元件被构造成使得由并联连接产生的电阻在预定的 温度范围和相应的制造方法。

公开(公告)号：US09269714B2

公开(公告)日：2016-02-23

申请号：US13914288

申请日：2013-06-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Illgen ,  Gerd Zschaezsch

IPC: H01L21/84 ,  H01L27/092 ,  H01L21/8238 ,  H01L27/12

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203

Abstract: A device includes a substrate, a P-channel transistor and an N-channel transistor. The substrate includes a first layer of a first semiconductor material and a second layer of a second semiconductor material. The first and second semiconductor materials have different crystal lattice constants. The P-channel transistor includes a channel region having a compressive stress in a first portion of the substrate. The channel region of the P-channel transistor includes a portion of the first layer of the first semiconductor material and a portion of the second layer of the second semiconductor material. The N-channel transistor includes a channel region having a tensile stress formed in a second portion of the substrate. The channel region of the N-channel transistor includes a portion of the first layer of the first semiconductor material and a portion of the second layer of the second semiconductor material. Methods of forming the device are also disclosed.

Abstract translation: 一种器件包括衬底，P沟道晶体管和N沟道晶体管。 衬底包括第一半导体材料的第一层和第二半导体材料的第二层。 第一和第二半导体材料具有不同的晶格常数。 P沟道晶体管包括在衬底的第一部分中具有压应力的沟道区。 P沟道晶体管的沟道区域包括第一半导体材料的第一层的一部分和第二半导体材料的第二层的一部分。 N沟道晶体管包括在衬底的第二部分中形成的具有拉伸应力的沟道区。 N沟道晶体管的沟道区域包括第一半导体材料的第一层的一部分和第二半导体材料的第二层的一部分。 还公开了形成装置的方法。

公开(公告)号：US09236440B2

公开(公告)日：2016-01-12

申请号：US14097338

申请日：2013-12-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Roman Boschke ,  Stefan Flachowsky ,  Elke Erben

IPC: H01L21/44 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/7833

Abstract: When forming field effect transistors, a common problem is the formation of a Schottky barrier at the interface between a metal thin film in the gate electrode and a semiconductor material, typically polysilicon, formed thereupon. Fully silicided gates are known in the state of the art which may overcome this problem. The claimed method proposes an improved fully silicided gate achieved by forming a gate structure including an additional metal layer between the metal gate layer and the gate semiconductor material. A silicidation process can then be optimized so as to form a lower metal silicide layer comprising the metal of the additional metal layer and an upper metal silicide layer forming an interface with the lower metal silicide layer.

Abstract translation: 当形成场效应晶体管时，常见的问题是在栅电极中的金属薄膜与其上形成的半导体材料（通常为多晶硅）之间的界面处形成肖特基势垒。 完全硅化的门在现有技术中是已知的，这可以克服这个问题。 所要求保护的方法提出了通过在金属栅极层和栅极半导体材料之间形成包括附加金属层的栅极结构而实现的改进的全硅化栅。 然后可以优化硅化工艺，以便形成包含附加金属层的金属和形成与下金属硅化物层的界面的上金属硅化物层的下金属硅化物层。

公开(公告)号：US09087587B2

公开(公告)日：2015-07-21

申请号：US13834019

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ricardo P. Mikalo ,  Stefan Flachowsky

IPC: G11C11/34 ,  G11C16/04 ,  H01L27/115

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  G11C16/045 ,  H01L27/11558 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/4916

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a semiconductor substrate doped with a first conductivity-determining impurity. The semiconductor substrate has formed therein a first well doped with a second conductivity-determining impurity that is different from the first conductivity-determining impurity, a second well, formed within the first well, and doped with the first conductivity-determining impurity, and a third well spaced apart from the first and second wells and doped with the second conductivity-determining impurity. The integrated circuit further includes a floating gate structure formed over the semiconductor substrate. The floating gate structure includes a first gate element disposed over the second well and being separated from the second well with a dielectric layer, a second gate element disposed over the third well and being separated from the third well with the dielectric layer, and a conductive connector.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，集成电路包括掺杂有第一导电性确定杂质的半导体衬底。 半导体衬底在其中形成有掺杂有与第一导电率确定杂质不同的第二导电率确定杂质的第一阱，形成在第一阱内的第二阱，并且掺杂有第一导电率确定杂质，以及 第三阱与第一和第二阱间隔开并掺杂有第二导电性确定杂质。 集成电路还包括形成在半导体衬底上的浮栅结构。 浮置栅极结构包括设置在第二阱上并与第二阱分离的第一栅极元件，其具有电介质层，第二栅极元件设置在第三阱上并与第三阱与介电层分离，并且导电 连接器。

公开(公告)号：US20150200270A1

公开(公告)日：2015-07-16

申请号：US14156861

申请日：2014-01-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Hermann Sachse ,  Maciej Wiatr

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/7816 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66575

Abstract: When forming semiconductor devices comprising high performance or low-power field effect transistors, the threshold voltage of the transistors is adjusted by the halo implantation and the source and drain regions are defined by a single implantation step. Thus, the number of process steps is reduced, whereas the electrical characteristics, such as leakage level, and performance of the transistors are maintained compared to conventional transistors.

Abstract translation: 当形成包括高性能或低功率场效应晶体管的半导体器件时，通过光晕注入来调节晶体管的阈值电压，并且通过单个注入步骤限定源极和漏极区域。 因此，与常规晶体管相比，工艺步骤的数量减少，而与诸如泄漏水平的电特性和晶体管的性能保持一致。

公开(公告)号：US09082662B2

公开(公告)日：2015-07-14

申请号：US13968545

申请日：2013-08-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thilo Scheiper ,  Stefan Flachowsky

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  H01L27/1207

Abstract: When forming sophisticated SOI devices, a substrate diode and a film diode are formed by using one and the same implantation mask for determining the well dopant concentration in the corresponding well regions. Consequently, during the further processing, the well dopant concentration of any transistor elements may be achieved independently from the well regions of the diode in the semiconductor layer.

Abstract translation: 当形成复杂的SOI器件时，通过使用一个相同的注入掩模来形成衬底二极管和膜二极管，以确定相应阱区中的阱掺杂剂浓度。 因此，在进一步处理期间，可以独立于半导体层中的二极管的阱区实现任何晶体管元件的阱掺杂剂浓度。

公开(公告)号：US09054044B2

公开(公告)日：2015-06-09

申请号：US13788719

申请日：2013-03-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Ralf Richter ,  Peter Javorka

IPC: H01L29/06 ,  H01L21/308 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/3083 ,  H01L29/0657 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

Abstract: Semiconductor device structures and methods for forming a semiconductor device are provided. In embodiments, one or more fins are provided, each of the one or more fins having a lower portion and an upper portion disposed on the lower portion. The lower portion is embedded in a first insulating material. The shape of the upper portion is at least one of a substantially triangular shape and a substantially rounded shape and a substantially trapezoidal shape. Furthermore, a layer of a second insulating material different from the first insulating material is formed on the upper portion.

Abstract translation: 提供了用于形成半导体器件的半导体器件结构和方法。 在实施例中，提供一个或多个翅片，所述一个或多个翅片中的每一个具有设置在下部的下部和上部。 下部嵌入第一绝缘材料中。 上部的形状是基本上三角形形状和大致圆形形状和大致梯形形状中的至少一个。 此外，在上部形成有与第一绝缘材料不同的第二绝缘材料层。

公开(公告)号：US20150097252A1

公开(公告)日：2015-04-09

申请号：US14047517

申请日：2013-10-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Roman Boschke

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L21/76805 ,  H01L21/823828 ,  H01L21/823835 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7833

Abstract: When forming field effect transistors according to the gate-first HKMG approach, the cap layer formed on top of the gate electrode had to be removed before the silicidation step, resulting in formation of a metal silicide layer on the surface of the gate electrode and of the source and drain regions of the transistor. The present disclosure improves the manufacturing flow by skipping the gate cap removal process. Metal silicide is only formed on the source and drain regions. The gate electrode is then contacted by forming an aperture through the gate material, leaving the surface of the gate metal layer exposed.

Abstract translation: 当根据栅极第一HKMG方法形成场效应晶体管时，形成在栅电极顶部上的覆盖层必须在硅化步骤之前去除，导致在栅电极的表面上形成金属硅化物层，并且 晶体管的源极和漏极区域。 本公开通过跳过栅极盖去除工艺来改善制造流程。 仅在源区和漏区形成金属硅化物。 然后通过形成通过栅极材料的孔而使栅电极接触，留下栅极金属层的表面。